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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove @ of vec_series
@ 2023-10-09 12:51 Jeff Law
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From: Jeff Law @ 2023-10-09 12:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a9e12b9e8ee3a08e32b119e2d66db1ff5811bc23
commit a9e12b9e8ee3a08e32b119e2d66db1ff5811bc23
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Wed Oct 4 23:01:15 2023 +0800
RISC-V: Remove @ of vec_series
gcc/ChangeLog:
* config/riscv/autovec.md (@vec_series<mode>): Remove @.
(vec_series<mode>): Ditto.
* config/riscv/riscv-v.cc (expand_const_vector): Ditto.
(shuffle_decompress_patterns): Ditto.
(cherry picked from commit 0bda3f25147203d04724fa375daf3d1110da5c3f)
Diff:
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/riscv-v.cc | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index d6cf376ebca..056f2c352f6 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -336,7 +336,7 @@
;; - vadd.vx/vadd.vi
;; -------------------------------------------------------------------------
-(define_expand "@vec_series<mode>"
+(define_expand "vec_series<mode>"
[(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VEL> 1 "reg_or_int_operand")
(match_operand:<VEL> 2 "reg_or_int_operand")]
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 29e138e1da2..23633a2a74d 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1014,7 +1014,7 @@ expand_const_vector (rtx target, rtx src)
rtx base, step;
if (const_vec_series_p (src, &base, &step))
{
- emit_insn (gen_vec_series (mode, target, base, step));
+ expand_vec_series (target, base, step);
return;
}
@@ -1171,7 +1171,7 @@ expand_const_vector (rtx target, rtx src)
rtx step = CONST_VECTOR_ELT (src, 2);
/* Step 1 - { base1, base1 + step, base1 + step * 2, ... } */
rtx tmp = gen_reg_rtx (mode);
- emit_insn (gen_vec_series (mode, tmp, base1, step));
+ expand_vec_series (tmp, base1, step);
/* Step 2 - { base0, base1, base1 + step, base1 + step * 2, ... } */
scalar_mode elem_mode = GET_MODE_INNER (mode);
if (!rtx_equal_p (base0, const0_rtx))
@@ -3020,7 +3020,7 @@ shuffle_decompress_patterns (struct expand_vec_perm_d *d)
/* Generate { 0, 1, .... } mask. */
rtx vid = gen_reg_rtx (sel_mode);
rtx vid_repeat = gen_reg_rtx (sel_mode);
- emit_insn (gen_vec_series (sel_mode, vid, const0_rtx, const1_rtx));
+ expand_vec_series (vid, const0_rtx, const1_rtx);
rtx and_ops[] = {vid_repeat, vid, const1_rtx};
emit_vlmax_insn (code_for_pred_scalar (AND, sel_mode), BINARY_OP, and_ops);
rtx const_vec = gen_const_vector_dup (sel_mode, 1);
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