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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Enable more tests of "vect" for RVV
@ 2023-10-09 12:52 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-10-09 12:52 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2bdf13fa4c9873fd99ea337e6fc73dcf5591f2b3
commit 2bdf13fa4c9873fd99ea337e6fc73dcf5591f2b3
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Sat Oct 7 15:04:58 2023 +0800
RISC-V: Enable more tests of "vect" for RVV
This patch enables almost full coverage vectorization tests for RVV, except these
following tests (not enabled yet):
1. Will enable soon:
check_effective_target_vect_call_lrint
check_effective_target_vect_call_btrunc
check_effective_target_vect_call_btruncf
check_effective_target_vect_call_ceil
check_effective_target_vect_call_ceilf
check_effective_target_vect_call_floor
check_effective_target_vect_call_floorf
check_effective_target_vect_call_lceil
check_effective_target_vect_call_lfloor
check_effective_target_vect_call_nearbyint
check_effective_target_vect_call_nearbyintf
check_effective_target_vect_call_round
check_effective_target_vect_call_roundf
2. Not sure we will need to enable or not:
check_effective_target_vect_complex_*
check_effective_target_vect_simd_clones
check_effective_target_vect_bswap
check_effective_target_vect_widen_shift
check_effective_target_vect_widen_mult_*
check_effective_target_vect_widen_sum_*
check_effective_target_vect_unpack
check_effective_target_vect_interleave
check_effective_target_vect_extract_even_odd
check_effective_target_vect_pack_trunc
check_effective_target_vect_check_ptrs
check_effective_target_vect_sdiv_pow2_si
check_effective_target_vect_usad_*
check_effective_target_vect_udot_*
check_effective_target_vect_sdot_*
check_effective_target_vect_gather_load_ifn
After this patch, we will have these following additional FAILs:
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1115.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1115.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s114.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s114.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1161.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1161.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1232.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1232.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s124.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s124.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1279.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1279.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s161.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s161.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s253.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s253.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s257.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s257.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s271.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s271.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2711.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2711.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2712.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2712.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s272.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s272.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s273.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s273.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s274.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s274.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s276.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s276.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s278.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s278.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s279.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s279.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s3111.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s3111.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s353.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s353.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s441.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s441.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s443.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-s443.c scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-vif.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops"
XPASS: gcc.dg/vect/tsvc/vect-tsvc-vif.c scan-tree-dump vect "vectorized 1 loops"
FAIL: gcc.dg/vect/vect-114.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorized 0 loops" 1
FAIL: gcc.dg/vect/vect-114.c scan-tree-dump-times vect "vectorized 0 loops" 1
FAIL: gcc.dg/vect/vect-live-2.c -flto -ffat-lto-objects scan-tree-dump-times vect "vec_stmt_relevant_p: stmt live but not relevant" 1
FAIL: gcc.dg/vect/vect-live-2.c scan-tree-dump-times vect "vec_stmt_relevant_p: stmt live but not relevant" 1
FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects scan-tree-dump vect "Reduce using vector shifts"
FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using vector shifts"
FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects scan-tree-dump vect "Reduce using vector shifts"
FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using vector shifts"
FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_ADD"
FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_SUB"
FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_MUL"
FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_RDIV"
They are all dump FAILs (No more ICE and execution FAILs).
Fixing those FAILs will be another separate patch.
But I think we should commit this patch first.
Ok for trunk ?
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Enable more vect tests for RVV.
(cherry picked from commit 752bfdb2bf0a4d84bc2fb2858410e9a97f4788d0)
Diff:
---
gcc/testsuite/lib/target-supports.exp | 141 +++++++++++++++++++++++++---------
1 file changed, 103 insertions(+), 38 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 1ba14a39205..3ec7ce9cd91 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3909,7 +3909,8 @@ proc check_effective_target_vect_int { } {
|| [et-is-effective-target mips_msa]))
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget riscv*-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v])
}}]
}
@@ -4037,7 +4038,9 @@ proc check_effective_target_vect_intfloat_cvt { } {
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*]
|| ([istarget s390*-*-*]
- && [check_effective_target_s390_vxe2]) }}]
+ && [check_effective_target_s390_vxe2])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports signed double->int conversion
@@ -4056,7 +4059,9 @@ proc check_effective_target_vect_doubleint_cvt { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
- && [check_effective_target_s390_vx]) }}]
+ && [check_effective_target_s390_vx])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports signed int->double conversion
@@ -4075,7 +4080,9 @@ proc check_effective_target_vect_intdouble_cvt { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
- && [check_effective_target_s390_vx]) }}]
+ && [check_effective_target_s390_vx])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
#Return 1 if we're supporting __int128 for target, 0 otherwise.
@@ -4106,7 +4113,9 @@ proc check_effective_target_vect_uintfloat_cvt { } {
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*]
|| ([istarget s390*-*-*]
- && [check_effective_target_s390_vxe2]) }}]
+ && [check_effective_target_s390_vxe2])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
@@ -4123,7 +4132,9 @@ proc check_effective_target_vect_floatint_cvt { } {
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*]
|| ([istarget s390*-*-*]
- && [check_effective_target_s390_vxe2]) }}]
+ && [check_effective_target_s390_vxe2])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports unsigned float->int conversion
@@ -4138,7 +4149,9 @@ proc check_effective_target_vect_floatuint_cvt { } {
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*]
|| ([istarget s390*-*-*]
- && [check_effective_target_s390_vxe2]) }}]
+ && [check_effective_target_s390_vxe2])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if peeling for alignment might be profitable on the target
@@ -7187,7 +7200,9 @@ proc check_effective_target_vect_shift { } {
|| [et-is-effective-target mips_loongson_mmi]))
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports hardware vector shift by register operation.
@@ -7197,6 +7212,8 @@ proc check_effective_target_vect_var_shift { } {
expr {(([istarget i?86-*-*] || [istarget x86_64-*-*])
&& [check_avx2_available])
|| [istarget aarch64*-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v])
}}]
}
@@ -7211,7 +7228,9 @@ proc check_effective_target_whole_vector_shift { } {
&& [et-is-effective-target mips_loongson_mmi])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] } {
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) } {
set answer 1
} else {
set answer 0
@@ -7237,7 +7256,9 @@ proc check_effective_target_vect_bool_cmp { } {
return [check_cached_effective_target_indexed vect_bool_cmp {
expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
|| [istarget aarch64*-*-*]
- || [is-effective-target arm_neon] }}]
+ || [is-effective-target arm_neon]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports addition of char vectors for at least
@@ -7258,6 +7279,8 @@ proc check_effective_target_vect_char_add { } {
|| [et-is-effective-target mips_msa]))
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v])
}}]
}
@@ -7272,7 +7295,9 @@ proc check_effective_target_vect_shift_char { } {
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports hardware vectors of long, 0 otherwise.
@@ -7291,7 +7316,9 @@ proc check_effective_target_vect_long { } {
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] } {
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) } {
set answer 1
} else {
set answer 0
@@ -7319,7 +7346,9 @@ proc check_effective_target_vect_float { } {
|| [is-effective-target arm_neon]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vxe])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports hardware vectors of float without
@@ -7348,7 +7377,9 @@ proc check_effective_target_vect_double { } {
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*]} }]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v])} }]
}
# Return 1 if the target supports conditional addition, subtraction,
@@ -7356,7 +7387,8 @@ proc check_effective_target_vect_double { } {
# via the cond_ optabs. Return 0 otherwise.
proc check_effective_target_vect_double_cond_arith { } {
- return [check_effective_target_aarch64_sve]
+ return [expr { [check_effective_target_aarch64_sve]
+ || [check_effective_target_riscv_v] }]
}
# Return 1 if the target supports hardware vectors of long long, 0 otherwise.
@@ -7373,7 +7405,9 @@ proc check_effective_target_vect_long_long { } {
|| ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*]
&& [check_effective_target_has_arch_pwr8])
- || [istarget aarch64*-*-*] }}]
+ || [istarget aarch64*-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v])}}]
}
@@ -7426,7 +7460,9 @@ proc check_effective_target_vect_perm { } {
|| [et-is-effective-target mips_msa]))
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if, for some VF:
@@ -7519,7 +7555,9 @@ proc check_effective_target_vect_perm_byte { } {
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports SLP permutation of 3 vectors when each
@@ -7548,7 +7586,9 @@ proc check_effective_target_vect_perm_short { } {
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports SLP permutation of 3 vectors when each
@@ -7813,8 +7853,10 @@ proc check_effective_target_vect_usad_char { } {
# and unsigned average operations on vectors of bytes.
proc check_effective_target_vect_avg_qi {} {
- return [expr { [istarget aarch64*-*-*]
- && ![check_effective_target_aarch64_sve1_only] }]
+ return [expr { ([istarget aarch64*-*-*]
+ && ![check_effective_target_aarch64_sve1_only])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }]
}
# Return 1 if the target plus current options supports both signed
@@ -8505,7 +8547,8 @@ proc check_effective_target_vect_load_lanes { } {
proc check_effective_target_vect_masked_load { } {
return [expr { [check_avx_available]
|| [check_effective_target_aarch64_sve]
- || [istarget amdgcn*-*-*] } ]
+ || [istarget amdgcn*-*-*]
+ || [check_effective_target_riscv_v] } ]
}
# Return 1 if the target supports vector masked stores.
@@ -8527,7 +8570,8 @@ proc check_effective_target_vect_gather_load_ifn { } {
proc check_effective_target_vect_scatter_store { } {
return [expr { [check_effective_target_aarch64_sve]
- || [istarget amdgcn*-*-*] }]
+ || [istarget amdgcn*-*-*]
+ || [check_effective_target_riscv_v] }]
}
# Return 1 if the target supports vector conditional operations, 0 otherwise.
@@ -8544,7 +8588,9 @@ proc check_effective_target_vect_condition { } {
&& [check_effective_target_arm_neon_ok])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports vector conditional operations where
@@ -8561,7 +8607,9 @@ proc check_effective_target_vect_cond_mixed { } {
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports vector char multiplication, 0 otherwise.
@@ -8577,7 +8625,9 @@ proc check_effective_target_vect_char_mult { } {
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports vector short multiplication, 0 otherwise.
@@ -8595,7 +8645,8 @@ proc check_effective_target_vect_short_mult { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
- || [istarget riscv*-*-*] }}]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports vector int multiplication, 0 otherwise.
@@ -8612,7 +8663,8 @@ proc check_effective_target_vect_int_mult { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
- || [istarget riscv*-*-*] }}]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports 64 bit hardware vector
@@ -8629,7 +8681,9 @@ proc check_effective_target_vect_long_mult { } {
|| ([istarget sparc*-*-*] && [check_effective_target_ilp32])
|| [istarget aarch64*-*-*]
|| ([istarget mips*-*-*]
- && [et-is-effective-target mips_msa]) } {
+ && [et-is-effective-target mips_msa])
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) } {
set answer 1
} else {
set answer 0
@@ -8643,8 +8697,11 @@ proc check_effective_target_vect_long_mult { } {
proc check_effective_target_vect_int_mod { } {
return [check_cached_effective_target_indexed vect_int_mod {
- expr { [istarget powerpc*-*-*]
- && [check_effective_target_has_arch_pwr10] }}]
+ expr { ([istarget powerpc*-*-*]
+ && [check_effective_target_has_arch_pwr10])
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports vector even/odd elements extraction, 0 otherwise.
@@ -8734,7 +8791,7 @@ proc available_vector_sizes { } {
lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
} elseif { [istarget riscv*-*-*] } {
if { [check_effective_target_riscv_v] } {
- lappend result 0 32
+ lappend result 0 32 64 128
}
lappend result 128
} else {
@@ -8775,7 +8832,9 @@ proc check_effective_target_vect_call_copysignf { } {
expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
|| [istarget powerpc*-*-*]
|| [istarget aarch64*-*-*]
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports hardware square root instructions.
@@ -8812,7 +8871,9 @@ proc check_effective_target_vect_call_sqrtf { } {
|| ([istarget powerpc*-*-*] && [check_vsx_hw_available])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || ([istarget riscv*-*-*]
+ && [check_effective_target_riscv_v]) }}]
}
# Return 1 if the target supports vector lrint calls.
@@ -8923,14 +8984,16 @@ proc check_effective_target_vect_call_roundf { } {
proc check_effective_target_vect_logical_reduc { } {
return [expr { [check_effective_target_aarch64_sve]
- || [istarget amdgcn-*-*] }]
+ || [istarget amdgcn-*-*]
+ || [check_effective_target_riscv_v] }]
}
# Return 1 if the target supports the fold_extract_last optab.
proc check_effective_target_vect_fold_extract_last { } {
return [expr { [check_effective_target_aarch64_sve]
- || [istarget amdgcn*-*-*] }]
+ || [istarget amdgcn*-*-*]
+ || [check_effective_target_riscv_v] }]
}
# Return 1 if the target supports section-anchors
@@ -9822,7 +9885,8 @@ proc check_effective_target_vect_sizes_32B_16B { } {
proc check_effective_target_vect_sizes_16B_8B { } {
if { [check_avx_available]
|| [is-effective-target arm_neon]
- || [istarget aarch64*-*-*] } {
+ || [istarget aarch64*-*-*]
+ || [check_effective_target_riscv_v] } {
return 1;
} else {
return 0;
@@ -11681,7 +11745,8 @@ proc check_effective_target_builtin_eh_return { } {
# Return 1 if the target supports max reduction for vectors.
proc check_effective_target_vect_max_reduc { } {
- if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] } {
+ if { [istarget aarch64*-*-*] || [is-effective-target arm_neon]
+ || [check_effective_target_riscv_v] } {
return 1
}
return 0
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2023-10-09 12:52 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Enable more tests of "vect" for RVV Jeff Law
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