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* [gcc r14-4609] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
@ 2023-10-13 6:03 Lehua Ding
0 siblings, 0 replies; only message in thread
From: Lehua Ding @ 2023-10-13 6:03 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2a89656a03282c0fe80c5467c6891c067ae0007a
commit r14-4609-g2a89656a03282c0fe80c5467c6891c067ae0007a
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Fri Oct 13 13:45:19 2023 +0800
RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
Like ARM SVE and GCN, add RVV.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
Diff:
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
index b348526b62f..f63b42a271a 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
@@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
/* Disable for SVE because for long or variable-length vectors we don't
get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD,
because there we can vectorize the epilogue using mixed vector sizes.
- Likewise for AMD GCN. */
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */
+ Likewise for AMD GCN and RVV. */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */
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2023-10-13 6:03 [gcc r14-4609] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV Lehua Ding
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