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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Change MD attribute avl_type into avl_type_idx[NFC]
@ 2023-10-30 18:32 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-10-30 18:32 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:69544a7cd8ec00ecb419acdcff3122b1194f8bfa
commit 69544a7cd8ec00ecb419acdcff3122b1194f8bfa
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Wed Oct 25 16:32:04 2023 +0800
RISC-V: Change MD attribute avl_type into avl_type_idx[NFC]
Address kito's comments of AVL propagation patch.
Change avl_type into avl_type_idx.
No functionality change.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (vlmax_avl_type_p): New function.
* config/riscv/riscv-v.cc (vlmax_avl_type_p): Ditto.
* config/riscv/riscv-vsetvl.cc (get_avl): Adapt function.
* config/riscv/vector.md: Change avl_type into avl_type_idx.
(cherry picked from commit 5e71499275525283f2255b4574599316b7ae8a78)
Diff:
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 12 +++
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
gcc/config/riscv/vector.md | 165 ++++++++++++++++++---------------------
4 files changed, 92 insertions(+), 88 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6cb9d459ee92..fffd9cd0b8af 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -559,6 +559,7 @@ bool cmp_lmul_le_one (machine_mode);
bool cmp_lmul_gt_one (machine_mode);
bool gather_scatter_valid_offset_mode_p (machine_mode);
bool vls_mode_valid_p (machine_mode);
+bool vlmax_avl_type_p (rtx_insn *);
}
/* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index e39a9507803f..d439ec06af02 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4435,4 +4435,16 @@ expand_popcount (rtx *ops)
emit_move_insn (dst, x4);
}
+/* Return true if it is VLMAX AVL TYPE. */
+bool
+vlmax_avl_type_p (rtx_insn *rinsn)
+{
+ extract_insn_cached (rinsn);
+ int index = get_attr_avl_type_idx (rinsn);
+ if (index == INVALID_ATTRIBUTE)
+ return false;
+ rtx avl_type = recog_data.operand[index];
+ return INTVAL (avl_type) == VLMAX;
+}
+
} // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index e9dd669de98e..73a6d4b74064 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -365,7 +365,7 @@ get_avl (rtx_insn *rinsn)
if (!has_vl_op (rinsn))
return NULL_RTX;
- if (get_attr_avl_type (rinsn) == VLMAX)
+ if (vlmax_avl_type_p (rinsn))
return RVV_VLMAX;
extract_insn_cached (rinsn);
return recog_data.operand[get_attr_vl_op_idx (rinsn)];
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index ef91950178f1..cea3dbf37a6e 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -800,31 +800,22 @@
(const_int INVALID_ATTRIBUTE)))
;; The avl type value.
-(define_attr "avl_type" ""
- (cond [(eq_attr "mode" "V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,
- V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI,
- V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,
- V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,
- V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,
- V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF,
- V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF,
- V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF")
- (symbol_ref "riscv_vector::NONVLMAX")
- (eq_attr "type" "vlde,vldff,vste,vimov,vimov,vimov,vfmov,vext,vimerge,\
+(define_attr "avl_type_idx" ""
+ (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vimov,vimov,vfmov,vext,vimerge,\
vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
vimovxv,vfmovfv,vlsegde,vlsegdff")
- (symbol_ref "INTVAL (operands[7])")
+ (const_int 7)
(eq_attr "type" "vldm,vstm,vimov,vmalu,vmalu")
- (symbol_ref "INTVAL (operands[5])")
+ (const_int 5)
;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
;; wheras it is pred_strided_load if operands[3] is vector mode.
(eq_attr "type" "vlds")
(if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
(const_int INVALID_ATTRIBUTE)
- (symbol_ref "INTVAL (operands[7])"))
+ (const_int 7))
(eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
@@ -832,18 +823,18 @@
vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
vlsegds,vlsegdux,vlsegdox")
- (symbol_ref "INTVAL (operands[8])")
+ (const_int 8)
(eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox")
- (symbol_ref "INTVAL (operands[5])")
+ (const_int 5)
(eq_attr "type" "vimuladd,vfmuladd")
- (symbol_ref "INTVAL (operands[9])")
+ (const_int 9)
(eq_attr "type" "vmsfs,vmidx,vcompress")
- (symbol_ref "INTVAL (operands[6])")
+ (const_int 6)
(eq_attr "type" "vmpop,vmffs,vssegte")
- (symbol_ref "INTVAL (operands[4])")]
+ (const_int 4)]
(const_int INVALID_ATTRIBUTE)))
;; Defines rounding mode of an fixed-point operation.
@@ -1209,7 +1200,7 @@
}
[(set_attr "type" "vmov,vlde,vste")
(set_attr "mode" "<VT:MODE>")
- (set (attr "avl_type") (const_int INVALID_ATTRIBUTE))])
+ (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))])
;; -----------------------------------------------------------------
;; ---- VLS Moves Operations
@@ -1668,7 +1659,7 @@
"vse<sew>.v\t%2,%0%p1"
[(set_attr "type" "vste")
(set_attr "mode" "<MODE>")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))
+ (set (attr "avl_type_idx") (const_int 4))
(set_attr "vl_op_idx" "3")])
;; vlm.v/vsm.v/vmclr.m/vmset.m.
@@ -1719,7 +1710,7 @@
"vsm.v\t%2,%0"
[(set_attr "type" "vstm")
(set_attr "mode" "<MODE>")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))
+ (set (attr "avl_type_idx") (const_int 4))
(set_attr "vl_op_idx" "3")])
(define_insn "@pred_merge<mode>"
@@ -2105,7 +2096,7 @@
vse<sew>.v\t%3,%0%p1"
[(set_attr "type" "vsts")
(set_attr "mode" "<MODE>")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
;; -------------------------------------------------------------------------------
;; ---- Predicated indexed loads/stores
@@ -2883,7 +2874,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "@pred_sbc<mode>"
[(set (match_operand:VI 0 "register_operand" "=vd,vd")
@@ -2907,7 +2898,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "@pred_adc<mode>_scalar"
[(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
@@ -2932,7 +2923,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "@pred_sbc<mode>_scalar"
[(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
@@ -2957,7 +2948,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_expand "@pred_adc<mode>_scalar"
[(set (match_operand:VI_D 0 "register_operand")
@@ -3014,7 +3005,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "*pred_adc<mode>_extended_scalar"
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
@@ -3040,7 +3031,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_expand "@pred_sbc<mode>_scalar"
[(set (match_operand:VI_D 0 "register_operand")
@@ -3097,7 +3088,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "*pred_sbc<mode>_extended_scalar"
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
@@ -3123,7 +3114,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "@pred_madc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
@@ -3142,7 +3133,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_insn "@pred_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
@@ -3161,7 +3152,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_insn "@pred_madc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3181,7 +3172,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_insn "@pred_msbc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3201,7 +3192,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_expand "@pred_madc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3249,7 +3240,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_insn "*pred_madc<mode>_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3270,7 +3261,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_expand "@pred_msbc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3318,7 +3309,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_insn "*pred_msbc<mode>_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3339,7 +3330,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_insn "@pred_madc<mode>_overflow"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
@@ -3357,7 +3348,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
(define_insn "@pred_msbc<mode>_overflow"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
@@ -3375,7 +3366,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
(define_insn "@pred_madc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3394,7 +3385,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
(define_insn "@pred_msbc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3413,7 +3404,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
(define_expand "@pred_madc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3459,7 +3450,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
(define_insn "*pred_madc<mode>_overflow_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3479,7 +3470,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
(define_expand "@pred_msbc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3525,7 +3516,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
(define_insn "*pred_msbc<mode>_overflow_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3545,7 +3536,7 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "avl_type_idx") (const_int 4))])
;; -------------------------------------------------------------------------------
;; ---- Predicated integer unary operations
@@ -3575,7 +3566,7 @@
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; -------------------------------------------------------------------------------
;; ---- Predicated integer widening binary operations
@@ -3826,7 +3817,7 @@
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; -------------------------------------------------------------------------------
;; ---- Predicated integer Narrowing operations
@@ -3902,7 +3893,7 @@
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; -------------------------------------------------------------------------------
;; ---- Predicated fixed-point operations
@@ -4374,7 +4365,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>"
@@ -4454,7 +4445,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_ltge<mode>"
@@ -4536,7 +4527,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
@@ -4620,7 +4611,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_eqne<mode>_scalar"
@@ -4759,7 +4750,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
@@ -4783,7 +4774,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
@@ -4892,7 +4883,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_extended_scalar"
@@ -4960,7 +4951,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_eqne<mode>_extended_scalar"
@@ -5208,7 +5199,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_insn "*pred_macc<mode>"
[(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
@@ -5239,7 +5230,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_expand "@pred_mul_plus<mode>_scalar"
[(set (match_operand:V_VLSI_QHS 0 "register_operand")
@@ -5292,7 +5283,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_insn "*pred_macc<mode>_scalar"
[(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
@@ -5324,7 +5315,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_expand "@pred_mul_plus<mode>_scalar"
[(set (match_operand:V_VLSI_D 0 "register_operand")
@@ -5391,7 +5382,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_insn "*pred_macc<mode>_extended_scalar"
[(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
@@ -5424,7 +5415,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_expand "@pred_minus_mul<mode>"
[(set (match_operand:V_VLSI 0 "register_operand")
@@ -5505,7 +5496,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_insn "*pred_nmsac<mode>"
[(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
@@ -5536,7 +5527,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_expand "@pred_minus_mul<mode>_scalar"
[(set (match_operand:V_VLSI_QHS 0 "register_operand")
@@ -5589,7 +5580,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_insn "*pred_nmsac<mode>_scalar"
[(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
@@ -5621,7 +5612,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_expand "@pred_minus_mul<mode>_scalar"
[(set (match_operand:V_VLSI_D 0 "register_operand")
@@ -5688,7 +5679,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
(define_insn "*pred_nmsac<mode>_extended_scalar"
[(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
@@ -5721,7 +5712,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type_idx") (const_int 8))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen integer ternary operations
@@ -5888,7 +5879,7 @@
[(set_attr "type" "vmalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "5")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))])
+ (set (attr "avl_type_idx") (const_int 6))])
(define_insn "@pred_n<optab><mode>"
[(set (match_operand:VB_VLS 0 "register_operand" "=vr")
@@ -5909,7 +5900,7 @@
[(set_attr "type" "vmalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "5")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))])
+ (set (attr "avl_type_idx") (const_int 6))])
(define_insn "@pred_<optab>not<mode>"
[(set (match_operand:VB_VLS 0 "register_operand" "=vr")
@@ -5930,7 +5921,7 @@
[(set_attr "type" "vmalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "5")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))])
+ (set (attr "avl_type_idx") (const_int 6))])
(define_insn "@pred_not<mode>"
[(set (match_operand:VB_VLS 0 "register_operand" "=vr")
@@ -5949,7 +5940,7 @@
[(set_attr "type" "vmalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "avl_type_idx") (const_int 5))])
(define_insn "@pred_popcount<VB:mode><P:mode>"
[(set (match_operand:P 0 "register_operand" "=r")
@@ -6368,7 +6359,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6403,7 +6394,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6462,7 +6453,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6498,7 +6489,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6592,7 +6583,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6628,7 +6619,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6689,7 +6680,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6726,7 +6717,7 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 8))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
@@ -6764,7 +6755,7 @@
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "avl_type_idx") (const_int 7))
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
@@ -6789,7 +6780,7 @@
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
(define_insn "@pred_<misc_op><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7178,7 +7169,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_cmp<mode>_narrow"
@@ -7240,7 +7231,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
@@ -7324,7 +7315,7 @@
(set_attr "merge_op_idx" "1")
(set_attr "vl_op_idx" "5")
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type_idx") (const_int 7))])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_eqne<mode>_scalar"
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2023-10-30 18:32 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Change MD attribute avl_type into avl_type_idx[NFC] Jeff Law
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