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* [gcc r14-5029] RISC-V: Add assert of the number of vmerge in autovec cond testcases
@ 2023-10-31 6:16 Lehua Ding
0 siblings, 0 replies; only message in thread
From: Lehua Ding @ 2023-10-31 6:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5ee961b6f26575cb3d29572fa5653bb65330d949
commit r14-5029-g5ee961b6f26575cb3d29572fa5653bb65330d949
Author: Lehua Ding <lehua.ding@rivai.ai>
Date: Tue Oct 31 11:50:42 2023 +0800
RISC-V: Add assert of the number of vmerge in autovec cond testcases
This patch adds more asserts about the vmerge insns which is intended
to ensure better performance for cond autovec.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Add vmerge assert.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: New test.
Diff:
---
.../riscv/rvv/autovec/cond/cond_arith-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-10.c | 63 ++++++++++++++++++++++
.../riscv/rvv/autovec/cond/cond_arith-11.c | 31 +++++++++++
.../riscv/rvv/autovec/cond/cond_arith-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-5.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-6.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-7.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-8.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith_run-10.c | 34 ++++++++++++
.../riscv/rvv/autovec/cond/cond_arith_run-11.c | 4 ++
.../autovec/cond/cond_convert_float2float-rv32-1.c | 1 +
.../autovec/cond/cond_convert_float2float-rv32-2.c | 1 +
.../autovec/cond/cond_convert_float2float-rv64-1.c | 1 +
.../autovec/cond/cond_convert_float2float-rv64-2.c | 1 +
.../autovec/cond/cond_convert_float2int-rv32-1.c | 1 +
.../autovec/cond/cond_convert_float2int-rv32-2.c | 1 +
.../autovec/cond/cond_convert_float2int-rv64-1.c | 1 +
.../autovec/cond/cond_convert_float2int-rv64-2.c | 1 +
.../autovec/cond/cond_convert_int2float-rv32-1.c | 2 +
.../autovec/cond/cond_convert_int2float-rv32-2.c | 2 +
.../autovec/cond/cond_convert_int2float-rv64-1.c | 2 +
.../autovec/cond/cond_convert_int2float-rv64-2.c | 2 +
.../rvv/autovec/cond/cond_convert_int2int-rv32-1.c | 2 +-
.../rvv/autovec/cond/cond_convert_int2int-rv32-2.c | 1 +
.../rvv/autovec/cond/cond_convert_int2int-rv64-1.c | 1 +
.../rvv/autovec/cond/cond_convert_int2int-rv64-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c | 1 +
.../riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-5.c | 39 +++++++-------
.../riscv/rvv/autovec/cond/cond_fma_fnma-6.c | 2 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-7.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-8.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c | 38 ++++++-------
.../riscv/rvv/autovec/cond/cond_fmax-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmax-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmax-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmax-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmin-1.c | 2 +-
.../riscv/rvv/autovec/cond/cond_fmin-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmin-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmin-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-4.c | 2 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-5.c | 2 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-6.c | 2 +
.../riscv/rvv/autovec/cond/cond_fmul-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-5.c | 29 ++++++++++
.../riscv/rvv/autovec/cond/cond_fmul_run-5.c | 33 ++++++++++++
.../rvv/autovec/cond/cond_logical_min_max-1.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-2.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-3.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-4.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-5.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-5.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-6.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-7.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-8.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-9.c | 1 +
.../riscv/rvv/autovec/cond/cond_sqrt-1.c | 2 +
.../riscv/rvv/autovec/cond/cond_sqrt-2.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-1.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-2.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-3.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-4.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-5.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-6.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-7.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-8.c | 2 +
87 files changed, 330 insertions(+), 40 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
index 922be4d7d349..afd73c25a894 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
@@ -59,3 +59,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
new file mode 100644
index 000000000000..f549b9e3aeae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define TEST(TYPE, NAME, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y, \
+ TYPE *__restrict z, TYPE *__restrict pred, \
+ TYPE *__restrict merged, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ x[i] = pred[i] != 1 ? y[i] OP z[i] : merged[i]; \
+ }
+
+#define TEST_TYPE(TYPE) \
+ TEST (TYPE, add, +) \
+ TEST (TYPE, sub, -) \
+ TEST (TYPE, mul, *) \
+ TEST (TYPE, div, /)
+
+#define TEST_TYPE2(TYPE) TEST (TYPE, rem, %)
+
+#define TEST_ALL \
+ TEST_TYPE (int8_t) \
+ TEST_TYPE (uint8_t) \
+ TEST_TYPE (int16_t) \
+ TEST_TYPE (uint16_t) \
+ TEST_TYPE (int32_t) \
+ TEST_TYPE (uint32_t) \
+ TEST_TYPE (int64_t) \
+ TEST_TYPE (uint64_t) \
+ TEST_TYPE2 (int8_t) \
+ TEST_TYPE2 (uint8_t) \
+ TEST_TYPE2 (int16_t) \
+ TEST_TYPE2 (uint16_t) \
+ TEST_TYPE2 (int32_t) \
+ TEST_TYPE2 (uint32_t) \
+ TEST_TYPE2 (int64_t) \
+ TEST_TYPE2 (uint64_t) \
+ TEST_TYPE (_Float16) \
+ TEST_TYPE (float) \
+ TEST_TYPE (double)
+
+TEST_ALL
+
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_ADD" 11 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_SUB" 11 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_MUL" 11 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_RDIV" 3 "optimized" } } */
+/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
new file mode 100644
index 000000000000..8b6ae61299c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include "cond_arith-1.c"
+
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */
+/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
index 986a70e45077..8b6ae61299c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
@@ -28,3 +28,4 @@
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
index a97d34facd8a..7f7d08a0806e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
@@ -68,3 +68,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
index 30089b784b97..8b1acea56a19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
@@ -22,3 +22,4 @@
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
index 2f9e883ff25f..d659f67f22c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
@@ -59,3 +59,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
index 13a230cca4f1..ef9e365d1cba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
@@ -28,3 +28,4 @@
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
index e43f040cd1a8..48c2a2b2bf3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
@@ -57,3 +57,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
index eac77e08b75d..375a7b9098ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
@@ -77,3 +77,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
new file mode 100644
index 000000000000..8e0d365fd198
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_arith-10.c"
+
+#define N 99
+
+#undef TEST
+#define TEST(TYPE, NAME, OP) \
+ { \
+ TYPE x[N], y[N], z[N], pred[N], merged[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ y[i] = i * i; \
+ z[i] = ((i + 2) % 3) * (i + 1); \
+ pred[i] = i % 3; \
+ merged[i] = i; \
+ } \
+ test_##TYPE##_##NAME (x, y, z, pred, merged, N); \
+ for (int i = 0; i < N; ++i) \
+ { \
+ TYPE expected = i % 3 != 1 ? y[i] OP z[i] : merged[i]; \
+ if (x[i] != expected) \
+ __builtin_abort (); \
+ asm volatile ("" ::: "memory"); \
+ } \
+ }
+
+int
+main (void)
+{
+ TEST_ALL
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
new file mode 100644
index 000000000000..b2da299f665d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_arith_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
index bb4873befdab..07512e5f40e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
index 4ec20e5ff23d..d2d1ea3678fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
index ec861fe16587..f793e93ecb14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
index 455a4b369532..79b835a69b4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
index 9dcbaa9b0a20..8cc0170edebd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
index 25d54247fede..44e990133ec2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
index 495f4b56a4d3..143e78c87d34 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
index 520c9df2dfb4..2d85a48ab2a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
index 030c8fe33ce6..a211192e83f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
@@ -15,3 +15,5 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
index 030c8fe33ce6..a211192e83f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
@@ -15,3 +15,5 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
index d6298f5351a8..4b3556988b78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
@@ -15,3 +15,5 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
index 23ad5f2b5791..42239ad2f6e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
@@ -15,3 +15,5 @@
/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
index 8c07e427560b..84988a70f7fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
@@ -14,4 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
-
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
index 74490cdc055d..2b6c72fa1920 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
index 00357966ba6c..e800abe9cf44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
index 3c4ad9c4f665..904e01c918a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
index cef531b97008..7340cc9e1af9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
@@ -10,3 +10,4 @@
/* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */
/* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
index cc2aa4de7578..471b56af7ad4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
@@ -10,3 +10,4 @@
/* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */
/* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
index c9d14f27e5dd..6f37680f0b4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
index 21f9f9f91078..eba1ab5d00f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
@@ -29,3 +29,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
index f71dbaa80ed9..c58eae9a2ca1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
index ffbe9a47cd9c..4ad7f7207396 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
index 0b19c54b562f..b4df366fd6ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
index bd61c0e2edcf..b2ac8e1844cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
index c011a290908a..6941a7bf911a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
index 98ba3c1a58d6..30cee819c6a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
index 98ba3c1a58d6..9b6a03e43e87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
@@ -1,30 +1,29 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
-#define DEF_LOOP(TYPE, NAME, OP) \
- void __attribute__ ((noipa)) \
- test_##TYPE##_##NAME (TYPE *__restrict r, \
- TYPE *__restrict a, \
- TYPE *__restrict b, TYPE c, \
- TYPE *__restrict pred, int n) \
- { \
- for (int i = 0; i < n; ++i) \
- r[i] = pred[i] == 1 ? a[i] OP b[i] * c : pred[i]; \
+#define DEF_LOOP(TYPE, NAME, OP) \
+ void __attribute__ ((noipa)) \
+ test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \
+ TYPE *__restrict b, TYPE c, TYPE *__restrict pred, \
+ TYPE *__restrict merged, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ r[i] = pred[i] == 1 ? a[i] OP b[i] * c : merged[i]; \
}
-#define TEST_TYPE(T, TYPE) \
- T (TYPE, add, +) \
+#define TEST_TYPE(T, TYPE) \
+ T (TYPE, add, +) \
T (TYPE, sub, -)
-#define TEST_ALL(T) \
- TEST_TYPE (T, uint8_t) \
- TEST_TYPE (T, uint16_t) \
- TEST_TYPE (T, uint32_t) \
- TEST_TYPE (T, uint64_t) \
- TEST_TYPE (T, _Float16) \
- TEST_TYPE (T, float) \
+#define TEST_ALL(T) \
+ TEST_TYPE (T, uint8_t) \
+ TEST_TYPE (T, uint16_t) \
+ TEST_TYPE (T, uint32_t) \
+ TEST_TYPE (T, uint64_t) \
+ TEST_TYPE (T, _Float16) \
+ TEST_TYPE (T, float) \
TEST_TYPE (T, double)
TEST_ALL (DEF_LOOP)
@@ -33,3 +32,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 14 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
index e72eb5e7603c..345f6efd2f1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
@@ -33,3 +33,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 14 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
index 3a69a59e8e8c..26a21793442a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
index 4df9da8ea4e2..f78fa094c817 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
index 3b0582d5939a..0fddce1bdc1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
@@ -6,25 +6,25 @@
#define FACTOR 17
#define N 99
-#define TEST_LOOP(TYPE, NAME, OP) \
- { \
- TYPE r[N], a[N], b[N], pred[N]; \
- for (int i = 0; i < N; ++i) \
- { \
- a[i] = (i & 1 ? i : 3 * i); \
- b[i] = (i >> 4) << (i & 15); \
- pred[i] = i % 3 < i % 5; \
- asm volatile ("" ::: "memory"); \
- } \
- test_##TYPE##_##NAME (r, a, b, FACTOR, pred, N); \
- for (int i = 0; i < N; ++i) \
- { \
- TYPE expected \
- = pred[i] ? a[i] OP b[i] * (TYPE) FACTOR : 0; \
- if (r[i] != expected) \
- __builtin_abort (); \
- asm volatile ("" ::: "memory"); \
- } \
+#define TEST_LOOP(TYPE, NAME, OP) \
+ { \
+ TYPE r[N], a[N], b[N], pred[N], merged[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i); \
+ b[i] = (i >> 4) << (i & 15); \
+ pred[i] = i % 3 < i % 5; \
+ merged[i] = i * 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ test_##TYPE##_##NAME (r, a, b, FACTOR, pred, merged, N); \
+ for (int i = 0; i < N; ++i) \
+ { \
+ TYPE expected = pred[i] ? a[i] OP b[i] * (TYPE) FACTOR : merged[i]; \
+ if (r[i] != expected) \
+ __builtin_abort (); \
+ asm volatile ("" ::: "memory"); \
+ } \
}
int
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
index fe37794afeb5..c5167b54fb33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
@@ -31,3 +31,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
index f25562b22ddc..30b6ae627773 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
index a23f4916caaa..4521f588f1ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
@@ -31,3 +31,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
index 79e4771eaf3a..251066e48849 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
@@ -31,3 +31,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
index f15964093121..9e3fd2904741 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
@@ -7,4 +7,4 @@
#include "cond_fmax-1.c"
/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
index 7c8c79ee251c..c48fab461ff1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
@@ -7,3 +7,4 @@
#include "cond_fmax-2.c"
/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
index aee0e3572b0f..e916008ebf0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
@@ -7,3 +7,4 @@
#include "cond_fmax-3.c"
/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
index 223c8a6938ba..2c2edc2933b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
@@ -7,3 +7,4 @@
#include "cond_fmax-4.c"
/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
index 2a28941eee2c..d3bf00e2a697 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
index d1826f3fde10..f593d5639722 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
index 57458239b802..cc23b1238534 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
index b5ed7045ae25..bd7b27a060e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
@@ -27,3 +27,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 3 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
index b5ed7045ae25..bd7b27a060e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
@@ -27,3 +27,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 3 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
index c5c8af86a815..bcb356e1df95 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
@@ -27,3 +27,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 3 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
index 94cec7ff0b16..9c9ed434cd0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
@@ -27,3 +27,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
index c8ada38c0025..3e7d1db7af2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
@@ -26,3 +26,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
index bd325ea84eea..e3c306d589b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
@@ -27,3 +27,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
index 118c9a40e8fd..57163ef36c6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
@@ -27,3 +27,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
new file mode 100644
index 000000000000..2e031a96215d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST) \
+ void __attribute__ ((noipa)) \
+ test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y, \
+ PRED_TYPE *__restrict pred, TYPE *__restrict merged, \
+ int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ x[i] = pred[i] != 1 ? y[i] * (TYPE) CONST : merged[i]; \
+ }
+
+#define TEST_TYPE(T, TYPE, PRED_TYPE) \
+ T (TYPE, PRED_TYPE, half, 0.5) \
+ T (TYPE, PRED_TYPE, two, 2.0) \
+ T (TYPE, PRED_TYPE, four, 4.0)
+
+#define TEST_ALL(T) \
+ TEST_TYPE (T, _Float16, int16_t) \
+ TEST_TYPE (T, float, int32_t) \
+ TEST_TYPE (T, double, int64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
new file mode 100644
index 000000000000..c3763b1f4bde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_fmul-5.c"
+
+#define N 99
+
+#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST) \
+ { \
+ TYPE x[N], y[N], merged[N]; \
+ PRED_TYPE pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ y[i] = i * i; \
+ pred[i] = i % 3; \
+ merged[i] = i; \
+ } \
+ test_##TYPE##_##NAME (x, y, pred, merged, N); \
+ for (int i = 0; i < N; ++i) \
+ { \
+ TYPE expected = i % 3 != 1 ? y[i] * (TYPE) CONST : merged[i]; \
+ if (x[i] != expected) \
+ __builtin_abort (); \
+ asm volatile ("" ::: "memory"); \
+ } \
+ }
+
+int
+main (void)
+{
+ TEST_ALL (TEST_LOOP)
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
index 703478610115..f90270263728 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
index 44cbbe61845e..70daec948478 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
index 220a37690dc2..72d498ede216 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
index 0763d9287897..a28bf57f1830 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
index 304c9eeb051b..03fb859af3e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
index 6bf25383deed..1c8a4cacf788 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
index 2edf38f89bd2..eb375ddb26d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
index 84f91ee26681..ab1c9e99c056 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
index a4be0b35aaf1..c7dd3dfc55dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
index 06a0a1aaecdc..cdaa3e1fe55b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
index 3b1c4859e05b..aa957ddaff95 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
@@ -25,3 +25,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
index d44cf43eeb0f..1f271c6dfb50 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
index e68289be5e07..f6dc7ff45bc0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
index 892bc08407d2..df3f390ea8d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
index ef17d3b25a76..d6b2f0f572f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
@@ -21,3 +21,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
index 5fbd63c32f93..1c5d3f0a1a4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
@@ -21,3 +21,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+
+/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
index cb738a84492f..28a5e025428b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
@@ -41,3 +41,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
index d9fb0865fc7f..e456e68e3275 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
@@ -44,3 +44,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
index 145839308e58..e2a873350793 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
@@ -41,3 +41,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
index e120e8f7e2ab..37c7ccb0d97f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
@@ -41,3 +41,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
index 775e65e7e6aa..2b4857fadbd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
@@ -34,3 +34,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
index 63314402fbde..4519a56d213f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
@@ -37,3 +37,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
index 4847aec49e09..0368f1c9a3ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
@@ -34,3 +34,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
index ae4d11893c9c..e3c19e46678e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
@@ -34,3 +34,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
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2023-10-31 6:16 [gcc r14-5029] RISC-V: Add assert of the number of vmerge in autovec cond testcases Lehua Ding
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