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* [gcc r14-6197] RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR
@ 2023-12-05 23:30 Pan Li
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From: Pan Li @ 2023-12-05 23:30 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2e7abd09621a4401d44f4513adf126bce4b4828b
commit r14-6197-g2e7abd09621a4401d44f4513adf126bce4b4828b
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Tue Dec 5 20:57:27 2023 +0800
RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR
This patch fixes ICE mentioned on PR112851 and PR112852.
Actually these ICEs happens many times in full coverage testing.
The ICE happens on:
bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187
84 | }
| ^
0x11a7271 partial_subreg_p(machine_mode, machine_mode)
../../../../gcc/gcc/rtl.h:3187
gcc_checking_assert (ordered_p (outer_prec, inner_prec));
outer_prec is the PRECISION of RVVM1SImode
inner_prec is the PRECISION of V64SImode
when it is zvl512b.
outer_prec is VLA mode with size (512, 512)
inner_prec is VLS mode with size (2048, 0)
Their precision/size relationship is not certain.
So block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR, then we never reaches
the situation that comparing the precision/size between VLA size and VLS size that size > coeffs[0] of VLA mode.
Note this patch cause following regression:
FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize scan-assembler-not vset
FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2
FAIL: gcc.target/riscv/rvv/base/cpymem-1.c check-function-bodies f3
FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f2
FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f3
1. cpymem check FAIL should be fixed on the testcase since the test is fragile which should be robostified.
2. pr111751.c is Vector cost model issue, and I will fix it in the following patch.
For now, we should land this patch first (highest-priority) since it is fixing ICE.
PR target/112851
PR target/112852
gcc/ChangeLog:
* config/riscv/riscv-v.cc (vls_mode_valid_p): Block VLSmodes according
TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/consecutive-1.c: Add LMUL = 8 option.
* gcc.target/riscv/rvv/autovec/vls/consecutive-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-13.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-14.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-17.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f-1.c: Adapt test.
* gcc.target/riscv/rvv/autovec/pr112851.c: New test.
* gcc.target/riscv/rvv/autovec/pr112852.c: New test.
Diff:
---
gcc/config/riscv/riscv-v.cc | 16 +++-
.../gcc.target/riscv/rvv/autovec/pr112851.c | 21 ++++++
.../gcc.target/riscv/rvv/autovec/pr112852.c | 87 ++++++++++++++++++++++
.../riscv/rvv/autovec/vls/consecutive-1.c | 2 +-
.../riscv/rvv/autovec/vls/consecutive-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mod-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-10.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-11.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-12.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-13.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-14.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-15.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-16.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-17.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-5.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-7.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-8.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/mov-9.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/spill-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/spill-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/spill-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/spill-5.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/spill-6.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f-1.c | 2 +-
26 files changed, 146 insertions(+), 24 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 87e50875308..71cb7567f1a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4051,7 +4051,21 @@ vls_mode_valid_p (machine_mode vls_mode)
return false;
if (riscv_autovec_preference == RVV_SCALABLE)
- return true;
+ {
+ if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL
+ && !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,
+ GET_MODE_PRECISION (vls_mode)))
+ /* We enable VLS modes which are aligned with TARGET_MAX_LMUL and
+ BITS_PER_RISCV_VECTOR.
+
+ e.g. When TARGET_MAX_LMUL = 1 and BITS_PER_RISCV_VECTOR = (128,128).
+ We enable VLS modes have fixed size <= 128bit. Since ordered_p is
+ false between VLA modes with size = (128, 128) bits and VLS mode
+ with size = 128 bits, we will end up with multiple ICEs in
+ middle-end generic codes. */
+ return false;
+ return true;
+ }
if (riscv_autovec_preference == RVV_FIXED_VLMAX)
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112851.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112851.c
new file mode 100644
index 00000000000..ff2e4faabbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112851.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions" } */
+
+int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,
+ safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,
+ g_97_l_439;
+void g_97(int * __restrict l_437)
+{
+ for (; g_97_l_439; g_97_l_439 += 1)
+ for (char l_502 = 0; l_502 < 4; l_502++)
+ {
+ int __trans_tmp_14 = ((safe_lshift_func_int32_t_s_s_right >= 2
+ || safe_lshift_func_int32_t_s_s_left)
+ ? 1 : safe_lshift_func_int32_t_s_s_right);
+ long __trans_tmp_15 = __trans_tmp_14 * safe_mul_func_uint64_t_u_u_ui2;
+ unsigned short __trans_tmp_16 = -__trans_tmp_15;
+ int __trans_tmp_7
+ = (__trans_tmp_16 ^ 65535UL) - safe_sub_func_uint64_t_u_u_ui2;
+ *l_437 ^= (short)(__trans_tmp_7 ^ g_79_2);
+ }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112852.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112852.c
new file mode 100644
index 00000000000..2d6e27e1831
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112852.c
@@ -0,0 +1,87 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -funroll-loops -ftracer" } */
+
+struct platform_device;
+typedef unsigned long __kernel_size_t;
+typedef unsigned short __u16;
+typedef unsigned int __u32;
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef __kernel_size_t size_t;
+typedef __u32 uint32_t;
+static inline __attribute__ ((always_inline))
+uint32_t __attribute__ ((pure)) bfin_dspid (void)
+{
+ return ( {
+ uint32_t __v; __v;}
+ );
+}
+struct list_head {
+ struct list_head *next, *prev;
+};
+struct page {
+ union {
+ };
+ struct list_head lru;
+};
+struct device_driver {
+ const char *name;
+ struct module *owner;
+};
+struct fb_info {
+ struct device *dev;
+};
+struct platform_driver {
+ int (*probe) (struct platform_device *);
+ int (*remove) (struct platform_device *);
+ struct device_driver driver;
+};
+struct firmware {
+ size_t size;
+ const u8 *data;
+};
+struct metronomefb_par {
+ struct fb_info *info;
+};
+struct waveform_hdr {
+ u8 trc;
+};
+static u8 calc_cksum (int start, int end, u8 * mem)
+{
+ u8 tmp = 0;
+ int i;
+ for (i = start; i < end; i++)
+ tmp += mem[i];
+ return tmp;
+}
+extern struct waveform_hdr *wfm_hdr;
+extern int wmta;
+
+static int
+load_waveform (u8 * mem, size_t size, int m, int t, struct metronomefb_par *par)
+{
+ int tta;
+ int trn = 0;
+ int i;
+ u8 cksum;
+ int cksum_idx;
+ struct device *dev = par->info->dev;
+ for (i = 0; i <= sizeof (*wfm_hdr) + wfm_hdr->trc; i++) {
+ if (mem[i] > t) {
+ trn = i - sizeof (*wfm_hdr) - 1;
+ }
+ }
+ tta = * (mem + wmta + m * 4) & 0x00FFFFFF;
+ cksum_idx = tta + trn * 4 + 3;
+ cksum = calc_cksum (cksum_idx - 3, cksum_idx, mem);
+ if (cksum != mem[cksum_idx]) {
+ __builtin_abort();
+ }
+}
+extern struct firmware *fw_entry;
+extern struct metronomefb_par *par;
+
+int metronomefb_probe (struct platform_device *dev)
+{
+ return load_waveform ((u8 *) fw_entry->data, fw_entry->size, 3, 31, par);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
index c010c883065..b9bc15f7c82 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
index ccbbb24ad5d..8c0bc201425 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
index c8caf353553..57bbf8fbc68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
index 24bb7240db8..18dad346464 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
index cae96b3be3f..c199c330ce5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
index e2ca21e2d5b..4737008426f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
index fc38e791ecf..f61c372162e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
index d51922efdc9..56a7cf0b9f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
index 8ed8f6be19e..de49ed82dbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
index f4ce5b3c0a6..bed6a4784b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
index ff36d785bc6..06ab31b3094 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
index 754771aa69d..c2f0e3c2fc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
index 86ce22896c5..77d3fed5886 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
index 04475207966..5fae343ed49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
index d0674a47a14..c515f022518 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
index b905c74d43b..1164ab5de9f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
index 5f9bc052e97..404ef5d0e86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
index 753fa254002..842bb630be5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
index e8fa54c1c12..8f6ee81b98f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
index 86a404cc2a4..0f317d6cce5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
index 7bff6e3cae8..b366a4649d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
index 1e4eca3aac6..d35e2a44f79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
index e0a4a1f58fd..ab57e89b1cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
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2023-12-05 23:30 [gcc r14-6197] RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR Pan Li
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