public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc r14-6211] RISC-V: Add vec_init expander for masks [PR112854].
@ 2023-12-06 10:16 Robin Dapp
0 siblings, 0 replies; only message in thread
From: Robin Dapp @ 2023-12-06 10:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:056cce412862f8d9b56a40dfbcbc3f9fa7f92883
commit r14-6211-g056cce412862f8d9b56a40dfbcbc3f9fa7f92883
Author: Robin Dapp <rdapp@ventanamicro.com>
Date: Tue Dec 5 15:24:12 2023 +0100
RISC-V: Add vec_init expander for masks [PR112854].
PR112854 shows a problem on rv32 with zvl1024b. During the course of
expand_constructor we try to overlay/subreg a 64-element mask by a
scalar (Pmode) register. This works for zvl512b and its maximum of
32 elements but fails for rv32 and 64 elements.
To circumvent this this patch adds a vec_init expander for vector masks
by initializing a QImode vector and comparing that against 0.
gcc/ChangeLog:
PR target/112854
PR target/112872
* config/riscv/autovec.md (vec_init<mode>qi): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112854.c: New test.
* gcc.target/riscv/rvv/autovec/pr112872.c: New test.
Diff:
---
gcc/config/riscv/autovec.md | 16 ++++++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c | 12 ++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c | 16 ++++++++++++++++
3 files changed, 44 insertions(+)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b9f7aa204da..55d3ae50c8b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -394,6 +394,22 @@
}
)
+;; Provide a vec_init for mask registers by initializing
+;; a QImode vector and comparing it against 0.
+(define_expand "vec_init<mode>qi"
+ [(match_operand:VB 0 "register_operand")
+ (match_operand 1 "")]
+ "TARGET_VECTOR"
+ {
+ machine_mode qimode = riscv_vector::get_vector_mode
+ (QImode, GET_MODE_NUNITS (<MODE>mode)).require ();
+ rtx tmp = gen_reg_rtx (qimode);
+ riscv_vector::expand_vec_init (tmp, operands[1]);
+ riscv_vector::expand_vec_cmp (operands[0], NE, tmp, CONST0_RTX (qimode));
+ DONE;
+ }
+)
+
;; Slide an RVV vector left and insert a scalar into element 0.
(define_expand "vec_shl_insert_<mode>"
[(match_operand:VI 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
new file mode 100644
index 00000000000..8f7f13f9dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+short a, b;
+void c(int d) {
+ for (; a; a--) {
+ b = 0;
+ for (; b <= 8; b++)
+ if (d)
+ break;
+ }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
new file mode 100644
index 00000000000..5c1d2188e12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+
+int a, c;
+char b;
+short d;
+void e() {
+ for (; d; d++) {
+ for (; c;)
+ ;
+ b = 3;
+ for (; b; b = 0)
+ if (a)
+ break;
+ }
+}
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2023-12-06 10:16 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-12-06 10:16 [gcc r14-6211] RISC-V: Add vec_init expander for masks [PR112854] Robin Dapp
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).