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* [gcc r14-6254] [APX NDD] Support APX NDD for cmove insns
@ 2023-12-07 1:40 Hongyu Wang
0 siblings, 0 replies; only message in thread
From: Hongyu Wang @ 2023-12-07 1:40 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:42cb34f94b1b6e78624320b0d5b564c8aa7bb030
commit r14-6254-g42cb34f94b1b6e78624320b0d5b564c8aa7bb030
Author: Hongyu Wang <hongyu.wang@intel.com>
Date: Wed Nov 8 16:04:26 2023 +0800
[APX NDD] Support APX NDD for cmove insns
gcc/ChangeLog:
* config/i386/i386.md (*mov<mode>cc_noc): Extend with new constraints
to support NDD.
(*movsicc_noc_zext): Likewise.
(*movsicc_noc_zext_1): Likewise.
(*movqicc_noc): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-ndd-cmov.c: New test.
Diff:
---
gcc/config/i386/i386.md | 48 +++++++++++++++++-----------
gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c | 16 ++++++++++
2 files changed, 45 insertions(+), 19 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 5c6275430d6..017ab720293 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -24417,47 +24417,56 @@
(neg:SWI (ltu:SWI (reg:CCC FLAGS_REG) (const_int 0))))])
(define_insn "*mov<mode>cc_noc"
- [(set (match_operand:SWI248 0 "register_operand" "=r,r")
+ [(set (match_operand:SWI248 0 "register_operand" "=r,r,r,r")
(if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:SWI248 2 "nonimmediate_operand" "rm,0")
- (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))]
+ (match_operand:SWI248 2 "nonimmediate_operand" "rm,0,rm,r")
+ (match_operand:SWI248 3 "nonimmediate_operand" "0,rm,r,rm")))]
"TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
+ cmov%O2%c1\t{%3, %0|%0, %3}
+ cmov%O2%C1\t{%2, %3, %0|%0, %3, %2}
+ cmov%O2%c1\t{%3, %2, %0|%0, %2, %3}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "<MODE>")])
(define_insn "*movsicc_noc_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm,0"))
+ (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm,r"))
(zero_extend:DI
- (match_operand:SI 3 "nonimmediate_operand" "0,rm"))))]
+ (match_operand:SI 3 "nonimmediate_operand" "0,rm,r,rm"))))]
"TARGET_64BIT
&& TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %k0|%k0, %2}
- cmov%O2%c1\t{%3, %k0|%k0, %3}"
- [(set_attr "type" "icmov")
+ cmov%O2%c1\t{%3, %k0|%k0, %3}
+ cmov%O2%C1\t{%2, %3, %k0|%k0, %3, %2}
+ cmov%O2%c1\t{%3, %2, %k0|%k0, %2, %3}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "SI")])
(define_insn "*movsicc_noc_zext_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r")
(zero_extend:DI
(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:SI 2 "nonimmediate_operand" "rm,0")
- (match_operand:SI 3 "nonimmediate_operand" "0,rm"))))]
+ (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm,r")
+ (match_operand:SI 3 "nonimmediate_operand" "0,rm,r,rm"))))]
"TARGET_64BIT
&& TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %k0|%k0, %2}
- cmov%O2%c1\t{%3, %k0|%k0, %3}"
- [(set_attr "type" "icmov")
+ cmov%O2%c1\t{%3, %k0|%k0, %3}
+ cmov%O2%C1\t{%2, %3, %k0|%k0, %3, %2}
+ cmov%O2%c1\t{%3, %2, %k0|%k0, %2, %3}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "SI")])
@@ -24482,14 +24491,15 @@
})
(define_insn "*movqicc_noc"
- [(set (match_operand:QI 0 "register_operand" "=r,r")
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:QI 2 "register_operand" "r,0")
- (match_operand:QI 3 "register_operand" "0,r")))]
+ (match_operand:QI 2 "register_operand" "r,0,r")
+ (match_operand:QI 3 "register_operand" "0,r,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
"#"
- [(set_attr "type" "icmov")
+ [(set_attr "isa" "*,*,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "QI")])
(define_split
diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c b/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c
new file mode 100644
index 00000000000..459dc965342
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -m64 -mapxf" } */
+/* { dg-final { scan-assembler-times "cmove\[^\n\r]*, %eax" 1 } } */
+/* { dg-final { scan-assembler-times "cmovge\[^\n\r]*, %eax" 1 } } */
+
+unsigned int c[4];
+
+unsigned long long foo1 (int a, unsigned int b)
+{
+ return a ? b : c[1];
+}
+
+unsigned int foo3 (int a, int b, unsigned int c, unsigned int d)
+{
+ return a < b ? c : d;
+}
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2023-12-07 1:40 [gcc r14-6254] [APX NDD] Support APX NDD for cmove insns Hongyu Wang
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