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* [gcc r14-8265] RISC-V: Tweak the wording for the sorry message
@ 2024-01-19 2:41 Kito Cheng
0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2024-01-19 2:41 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:565935f93a7da629da89b05812a3e8c43287598f
commit r14-8265-g565935f93a7da629da89b05812a3e8c43287598f
Author: Kito Cheng <kito.cheng@sifive.com>
Date: Fri Jan 19 10:30:16 2024 +0800
RISC-V: Tweak the wording for the sorry message
Use "does not" rather than "cannot", because it's implementation issue.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_override_options_internal): Tweak
sorry message.
Diff:
---
gcc/config/riscv/riscv.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f1d5129397f..dd6e68a08c2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
- sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
+ sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
"'V' Extension");
/* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
big-endian after finishing full coverage testing. */
if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
- sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+ sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
/* Convert -march to a chunks count. */
riscv_vector_chunks = riscv_convert_vector_bits (opts);
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