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* [gcc(refs/users/meissner/heads/work154-vsubreg)] Peter's patches for subreg support.
@ 2024-01-23 7:16 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2024-01-23 7:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4ebb3f02439b618c5859df6887d16fe9abe01c5c
commit 4ebb3f02439b618c5859df6887d16fe9abe01c5c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 23 02:14:45 2024 -0500
Peter's patches for subreg support.
2024-01-23 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/109116
* gcc/config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Make OOmode
tieable with 128-bit vector modes.
2024-01-23 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/109116
* gcc/config/rs6000/mma.md (vsx_disassemble_pair): Use SUBREG's instead
of UNSPEC's.
(mma_disassemble_acc): Likewise.
Diff:
---
gcc/config/rs6000/mma.md | 50 ++++-----------------------------------------
gcc/config/rs6000/rs6000.cc | 9 +++++---
2 files changed, 10 insertions(+), 49 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 04e2d0066df..c3764f54b27 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -398,29 +398,8 @@
(match_operand 2 "const_0_to_1_operand")]
"TARGET_MMA"
{
- rtx src;
- int regoff = INTVAL (operands[2]);
- src = gen_rtx_UNSPEC (V16QImode,
- gen_rtvec (2, operands[1], GEN_INT (regoff)),
- UNSPEC_MMA_EXTRACT);
- emit_move_insn (operands[0], src);
- DONE;
-})
-
-(define_insn_and_split "*vsx_disassemble_pair"
- [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa")
- (unspec:V16QI [(match_operand:OO 1 "vsx_register_operand" "wa")
- (match_operand 2 "const_0_to_1_operand")]
- UNSPEC_MMA_EXTRACT))]
- "TARGET_MMA
- && vsx_register_operand (operands[1], OOmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- int reg = REGNO (operands[1]);
- int regoff = INTVAL (operands[2]);
- rtx src = gen_rtx_REG (V16QImode, reg + regoff);
+ int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode);
+ rtx src = simplify_gen_subreg (V16QImode, operands[1], OOmode, regoff);
emit_move_insn (operands[0], src);
DONE;
})
@@ -472,29 +451,8 @@
(match_operand 2 "const_0_to_3_operand")]
"TARGET_MMA"
{
- rtx src;
- int regoff = INTVAL (operands[2]);
- src = gen_rtx_UNSPEC (V16QImode,
- gen_rtvec (2, operands[1], GEN_INT (regoff)),
- UNSPEC_MMA_EXTRACT);
- emit_move_insn (operands[0], src);
- DONE;
-})
-
-(define_insn_and_split "*mma_disassemble_acc"
- [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa")
- (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
- (match_operand 2 "const_0_to_3_operand")]
- UNSPEC_MMA_EXTRACT))]
- "TARGET_MMA
- && fpr_reg_operand (operands[1], XOmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- int reg = REGNO (operands[1]);
- int regoff = INTVAL (operands[2]);
- rtx src = gen_rtx_REG (V16QImode, reg + regoff);
+ int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode);
+ rtx src = simplify_gen_subreg (V16QImode, operands[1], XOmode, regoff);
emit_move_insn (operands[0], src);
DONE;
})
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 5d975dab921..50a9bcd71c8 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1973,9 +1973,12 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
static bool
rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
- if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode
- || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode)
- return mode1 == mode2;
+ if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode
+ || mode2 == PTImode || mode2 == XOmode)
+ return mode1 == mode2;
+
+ if (mode2 == OOmode)
+ return ALTIVEC_OR_VSX_VECTOR_MODE (mode1);
if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work154-vsubreg)] Peter's patches for subreg support.
@ 2024-01-23 7:19 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2024-01-23 7:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4b211ff7e6eae16d7d26102bb0ce185969f6bd0c
commit 4b211ff7e6eae16d7d26102bb0ce185969f6bd0c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 23 02:14:45 2024 -0500
Peter's patches for subreg support.
2024-01-23 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/109116
* gcc/config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Make OOmode
tieable with 128-bit vector modes.
2024-01-23 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/109116
* gcc/config/rs6000/mma.md (vsx_disassemble_pair): Use SUBREG's instead
of UNSPEC's.
(mma_disassemble_acc): Likewise.
Diff:
---
gcc/config/rs6000/mma.md | 50 ++++-----------------------------------------
gcc/config/rs6000/rs6000.cc | 9 +++++---
2 files changed, 10 insertions(+), 49 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 6a7d8a836db..831e646c473 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -405,29 +405,8 @@
(match_operand 2 "const_0_to_1_operand")]
"TARGET_MMA"
{
- rtx src;
- int regoff = INTVAL (operands[2]);
- src = gen_rtx_UNSPEC (V16QImode,
- gen_rtvec (2, operands[1], GEN_INT (regoff)),
- UNSPEC_MMA_EXTRACT);
- emit_move_insn (operands[0], src);
- DONE;
-})
-
-(define_insn_and_split "*vsx_disassemble_pair"
- [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa")
- (unspec:V16QI [(match_operand:OO 1 "vsx_register_operand" "wa")
- (match_operand 2 "const_0_to_1_operand")]
- UNSPEC_MMA_EXTRACT))]
- "TARGET_MMA
- && vsx_register_operand (operands[1], OOmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- int reg = REGNO (operands[1]);
- int regoff = INTVAL (operands[2]);
- rtx src = gen_rtx_REG (V16QImode, reg + regoff);
+ int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode);
+ rtx src = simplify_gen_subreg (V16QImode, operands[1], OOmode, regoff);
emit_move_insn (operands[0], src);
DONE;
})
@@ -479,29 +458,8 @@
(match_operand 2 "const_0_to_3_operand")]
"TARGET_MMA"
{
- rtx src;
- int regoff = INTVAL (operands[2]);
- src = gen_rtx_UNSPEC (V16QImode,
- gen_rtvec (2, operands[1], GEN_INT (regoff)),
- UNSPEC_MMA_EXTRACT);
- emit_move_insn (operands[0], src);
- DONE;
-})
-
-(define_insn_and_split "*mma_disassemble_acc"
- [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa")
- (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
- (match_operand 2 "const_0_to_3_operand")]
- UNSPEC_MMA_EXTRACT))]
- "TARGET_MMA
- && fpr_reg_operand (operands[1], XOmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- int reg = REGNO (operands[1]);
- int regoff = INTVAL (operands[2]);
- rtx src = gen_rtx_REG (V16QImode, reg + regoff);
+ int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode);
+ rtx src = simplify_gen_subreg (V16QImode, operands[1], XOmode, regoff);
emit_move_insn (operands[0], src);
DONE;
})
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 68a14c6f88a..f3aa1c15f68 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1973,9 +1973,12 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
static bool
rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
- if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode
- || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode)
- return mode1 == mode2;
+ if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode
+ || mode2 == PTImode || mode2 == XOmode)
+ return mode1 == mode2;
+
+ if (mode2 == OOmode)
+ return ALTIVEC_OR_VSX_VECTOR_MODE (mode1);
if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2024-01-23 7:19 UTC | newest]
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