[gcc(refs/vendors/ARM/heads/gcs)] aarch64: Add support for chkfeat insn

[gcc(refs/vendors/ARM/heads/gcs)] aarch64: Add support for chkfeat insn

[Szabolcs Nagy]

https://gcc.gnu.org/g:3e65859dae0437d51d8e0aba24471fa11ec1aeeb

commit 3e65859dae0437d51d8e0aba24471fa11ec1aeeb
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Tue May 9 15:37:49 2023 +0100

    aarch64: Add support for chkfeat insn
    
    This is a hint space instruction to check for enabled HW features and
    update the x16 register accordingly.
    
    Use unspec_volatile to prevent reordering it around calls since calls
    can enable or disable HW features.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.md (aarch64_chkfeat): New.

Diff:
---
 gcc/config/aarch64/aarch64.md | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 15b08ab19819..3a3dc9ac6fe6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -378,6 +378,7 @@
     UNSPECV_BTI_C		; Represent BTI c.
     UNSPECV_BTI_J		; Represent BTI j.
     UNSPECV_BTI_JC		; Represent BTI jc.
+    UNSPECV_CHKFEAT		; Represent CHKFEAT X16.
     UNSPECV_TSTART		; Represent transaction start.
     UNSPECV_TCOMMIT		; Represent transaction commit.
     UNSPECV_TCANCEL		; Represent transaction cancel.
@@ -8253,6 +8254,14 @@
   "msr\tnzcv, %0"
 )
 
+;; CHKFEAT instruction
+(define_insn "aarch64_chkfeat"
+  [(set (reg:DI R16_REGNUM)
+        (unspec_volatile:DI [(reg:DI R16_REGNUM)] UNSPECV_CHKFEAT))]
+  ""
+  "hint\\t40 // chkfeat x16"
+)
+
 ;; AdvSIMD Stuff
 (include "aarch64-simd.md")

[gcc(refs/vendors/ARM/heads/gcs)] aarch64: Add support for chkfeat insn

[Szabolcs Nagy]

https://gcc.gnu.org/g:309f26c530aaaa1d11891a6adddf9515adf5a9b0

commit 309f26c530aaaa1d11891a6adddf9515adf5a9b0
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Tue May 9 15:37:49 2023 +0100

    aarch64: Add support for chkfeat insn
    
    This is a hint space instruction to check for enabled HW features and
    update the x16 register accordingly.
    
    Use unspec_volatile to prevent reordering it around calls since calls
    can enable or disable HW features.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.md (aarch64_chkfeat): New.

Diff:
---
 gcc/config/aarch64/aarch64.md | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 385a669b9b3..a20462303b5 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -378,6 +378,7 @@
     UNSPECV_BTI_C		; Represent BTI c.
     UNSPECV_BTI_J		; Represent BTI j.
     UNSPECV_BTI_JC		; Represent BTI jc.
+    UNSPECV_CHKFEAT		; Represent CHKFEAT X16.
     UNSPECV_TSTART		; Represent transaction start.
     UNSPECV_TCOMMIT		; Represent transaction commit.
     UNSPECV_TCANCEL		; Represent transaction cancel.
@@ -8258,6 +8259,14 @@
   "msr\tnzcv, %0"
 )
 
+;; CHKFEAT instruction
+(define_insn "aarch64_chkfeat"
+  [(set (reg:DI R16_REGNUM)
+        (unspec_volatile:DI [(reg:DI R16_REGNUM)] UNSPECV_CHKFEAT))]
+  ""
+  "hint\\t40 // chkfeat x16"
+)
+
 ;; AdvSIMD Stuff
 (include "aarch64-simd.md")