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* [gcc(refs/users/meissner/heads/work158-dmf)] Add -mcpu=future patches.
@ 2024-02-14 23:28 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2024-02-14 23:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:709fcf5351790fed0883262bfade422a03cb790c
commit 709fcf5351790fed0883262bfade422a03cb790c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Feb 14 18:19:04 2024 -0500
Add -mcpu=future patches.
Late in the development of power10, we discovered that there were some issues
in using load vector pair and store vector pair instructions to do memory
copies, so the defaults were modified to not use these instructions. This
patch re-enables using load and store vector pair instructions.
Previously the -mblock-ops-vector-pair switch was not set in POWERPC_MASKS.
This means the option was not reset if the cpu was changed via target
attributes or targt pragmas. I added this mask to POWERPC_MASKS since the
option is set via -mcpu=future.
This patch uses the .machine directive to tell the assembler to use any
possible future instructions.
This patch makes -mcpu=future act like -mcpu=power10 in terms of tuning. If
future patches changes the tuning, then this patch woucl be changed to use the
new tuning information. Until there is different tuning, this patch does not
allow the user to explicitly use -mtune=future.
This patch passes -mfuture to the assembler if the user used -mcpu=future.
This patch defines _ARCH_PWR_FUTURE if -mcpu=future was used.
This patch prints that -mcpu=future was selected if you use the debugging
switch -mdebug=reg.
This patch adds the basic support for -mcpu=future, which is a framework to add
support for possible future PowerPCs. This patch is only sets the future bit
in the ISA options.
2024-02-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Turn on
-mblock-ops-vector-pair for -mcpu=future.
(POWERPC_MASKS): Add -mblock-ops-vector-pair.
2024-02-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Output .machine
future if -mcpu=future.
2024-02-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Make
-mtune=future become -mtune=power10.
2024-02-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.h (ASM_CPU_SPEC): If -mcpu=future, pass -mfuture
to the assembler.
2024-02-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
2024-02-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_opt_masks): Add entry to print out
-mfuture in the isa flags.
2024-02-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New option
bits for -mcpu=future.
(POWERPC_MASKS): Add -mfuture mask.
(future cpu): Add -mcpu=future.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New processor type.
* config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Likewise.
* config/rs6000/rs6000.opt (-mfuture): New insert mask for -mcpu=future.
* doc/invoke.texi (PowerPC options): Add -mcpu=future.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 8 ++++++++
gcc/config/rs6000/rs6000-opts.h | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 31 +++++++++++++++++++++++++++++--
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 4 ++++
gcc/doc/invoke.texi | 2 +-
9 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d373..f2fb5bef678c 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+ if ((flags & OPTION_MASK_FUTURE) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index d28cc87eb2a1..ed934e0213e5 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -88,6 +88,11 @@
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
+/* Flags for a potential future processor that may or may not be delivered. */
+#define ISA_FUTURE_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
+ | OPTION_MASK_FUTURE)
+
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_P9_MINMAX)
@@ -123,6 +128,7 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
+ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
@@ -135,6 +141,7 @@
| OPTION_MASK_LOAD_VECTOR_PAIR \
| OPTION_MASK_POWER10 \
| OPTION_MASK_P10_FUSION \
+ | OPTION_MASK_FUTURE \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
@@ -267,3 +274,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 33fd0efc936f..b2ae180c0f05 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -62,6 +62,7 @@ enum processor_type
PROCESSOR_POWER8,
PROCESSOR_POWER9,
PROCESSOR_POWER10,
+ PROCESSOR_FUTURE,
PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 65f46709716f..97fa98a2e65e 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
EnumValue
Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
+EnumValue
+Enum(rs6000_cpu_opt_value) String(future) Value(57)
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 68a14c6f88a3..6bd537836d1b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3756,16 +3756,40 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_POWERPC64;
#endif
+ /* At the moment, we don't have explicit -mtune=future support. If the user
+ explicitly uses -mtune=future, give a warning. If not, use the power10
+ tuning until future tuning is added. */
if (rs6000_tune_index >= 0)
- tune_index = rs6000_tune_index;
+ {
+ enum processor_type cur_proc
+ = processor_target_table[rs6000_tune_index].processor;
+
+ if (cur_proc == PROCESSOR_FUTURE)
+ {
+ warning (0, "%qs is not currently supported", "-mtune=future");
+ rs6000_tune_index = rs6000_cpu_name_lookup ("power10");
+ }
+ tune_index = rs6000_tune_index;
+ }
else if (cpu_index >= 0)
- rs6000_tune_index = tune_index = cpu_index;
+ {
+ enum processor_type cur_cpu
+ = processor_target_table[cpu_index].processor;
+
+ rs6000_tune_index = tune_index
+ = (cur_cpu == PROCESSOR_FUTURE
+ ? rs6000_cpu_name_lookup ("power10")
+ : cpu_index);
+ }
else
{
size_t i;
enum processor_type tune_proc
= (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
+ if (tune_proc == PROCESSOR_FUTURE)
+ tune_proc = PROCESSOR_POWER10;
+
tune_index = -1;
for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
if (processor_target_table[i].processor == tune_proc)
@@ -5944,6 +5968,8 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
+ if ((flags & (ISA_FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+ return "future";
if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
return "power10";
if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -24505,6 +24531,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
{ "power10", OPTION_MASK_POWER10, false, true },
+ { "future", OPTION_MASK_FUTURE, false, true },
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2291fe8d3a34..43209f9a6e72 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -163,6 +163,7 @@
mcpu=e5500: -me5500; \
mcpu=e6500: -me6500; \
mcpu=titan: -mtitan; \
+ mcpu=future: -mfuture; \
!mcpu*: %{mpower9-vector: -mpower9; \
mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
mvsx: -mpower7; \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4acb4031ae08..bd0ecdd90070 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -350,7 +350,7 @@
ppc750,ppc7400,ppc7450,
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
- power4,power5,power6,power7,power8,power9,power10,
+ power4,power5,power6,power7,power8,power9,power10,future,
rs64a,mpccore,cell,ppca2,titan"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 60b923f5e4b3..4ad1d8e302c0 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -612,6 +612,10 @@ mrop-protect
Target Var(rs6000_rop_protect) Init(0)
Enable instructions that guard against return-oriented programming attacks.
+mfuture
+Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
+Generate (do not generate) store vector pair instructions.
+
mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 71339b8b30fa..dcc9f82171c8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31091,7 +31091,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
+@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}.
@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
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