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* [gcc(refs/users/meissner/heads/work158-pnext)] Add -mcpu=power11 support.
@ 2024-02-15 23:44 Michael Meissner
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From: Michael Meissner @ 2024-02-15 23:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:692c39f8033f9a9cce7e2f4b28c9a1fbbccde155
commit 692c39f8033f9a9cce7e2f4b28c9a1fbbccde155
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Feb 15 18:43:46 2024 -0500
Add -mcpu=power11 support.
2024-02-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config.gcc (powerpc*-*-*, rs6000-*-*): Add support for
--with-cpu=power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New macro.
(POWERPC_MASKS): Add -mcpu=power11 ISA bit.
(power11 cpu): New cpu target.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Define as
PROCESSOR_POWER10 for now.
* config/rs6000/rs6000-tables.optL: Regenerate.
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Set .machine
power11 if -mcpu=power11.
(rs6000_opt_masks): Add Power11.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mpower11 to the assembler
if -mcpu=power11.
* config/rs6000/rs6000.opt (-mpower11): Add ISA bit for power11.
* doc/invoke.texi (PowerPC options): Document -mcpu=power11.
Diff:
---
gcc/config.gcc | 5 +++--
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 8 +++++++-
gcc/config/rs6000/rs6000-opts.h | 5 +++--
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 3 +++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.opt | 3 +++
gcc/doc/invoke.texi | 5 +++--
9 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8dac5931e7f0..421d2482d248 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -530,7 +530,8 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|future)
+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|\
+ xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5554,7 +5555,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le | future \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index f2fb5bef678c..d15bb85743c1 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+ if ((flags & OPTION_MASK_POWER11) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
if ((flags & OPTION_MASK_FUTURE) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index ed934e0213e5..40c2b2917749 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -88,8 +88,12 @@
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
+/* Flags for a Power11 processor. */
+#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_POWER11)
+
/* Flags for a potential future processor that may or may not be delivered. */
-#define ISA_FUTURE_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+#define ISA_FUTURE_MASKS_SERVER (ISA_POWER11_MASKS_SERVER \
| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_FUTURE)
@@ -140,6 +144,7 @@
| OPTION_MASK_FPRND \
| OPTION_MASK_LOAD_VECTOR_PAIR \
| OPTION_MASK_POWER10 \
+ | OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_FUTURE \
| OPTION_MASK_HTM \
@@ -275,3 +280,4 @@ RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
+RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index e4e90a1603d6..1fe228dae296 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -70,8 +70,9 @@ enum processor_type
PROCESSOR_TITAN
};
-/* Until there are changes for -mcpu=future, treat -mcpu=future to be like
- -mcpu=power10. */
+/* Until there are changes for either -mcpu=future or -mcpu=power11, treat them
+ to be like -mcpu=power10. */
+#define PROCESSOR_POWER11 PROCESSOR_POWER10
#define PROCESSOR_FUTURE PROCESSOR_POWER10
/* Types of costly dependences. */
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 97fa98a2e65e..2c96e3aa1bd2 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -200,3 +200,6 @@ Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
EnumValue
Enum(rs6000_cpu_opt_value) String(future) Value(57)
+EnumValue
+Enum(rs6000_cpu_opt_value) String(power11) Value(58)
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 83ae71e165dd..39ec1ed9ab67 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5946,6 +5946,8 @@ rs6000_machine_from_flags (void)
if ((flags & OPTION_MASK_FUTURE) != 0)
return "future";
+ if ((flags & OPTION_MASK_POWER11) != 0)
+ return "power11";
if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
return "power10";
if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -24529,6 +24531,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
+ { "power11", OPTION_MASK_POWER11, false, false },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "prefixed", OPTION_MASK_PREFIXED, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 43209f9a6e72..5ad2adbdace5 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -107,6 +107,7 @@
to the assembler if -mpower9-vector was also used. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpower11; \
mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 059337c50d70..144173613102 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -612,6 +612,9 @@ mrop-protect
Target Var(rs6000_rop_protect) Init(0)
Enable instructions that guard against return-oriented programming attacks.
+mpower11
+Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
+
mfuture
Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dcc9f82171c8..85747e04ec8a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31090,8 +31090,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}.
+@samp{power9}, @samp{power10}, @samp{power11},
+@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
+@samp{rs64}, @samp{future}, and @samp{native}.
@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
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