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* [gcc(refs/users/meissner/heads/work159)] Add -mcpu=power11 and -mcpu=future support.
@ 2024-02-21 19:01 Michael Meissner
  0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2024-02-21 19:01 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:0a2a067b87f0c77c44fddf343f05d4fb7c6243f3

commit 0a2a067b87f0c77c44fddf343f05d4fb7c6243f3
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Feb 21 13:36:54 2024 -0500

    Add -mcpu=power11 and -mcpu=future support.
    
    This patch adds support for -mcpu=power11 and -mtune=power11.  At the current
    time, no new instructions are implemented.  The tuning for the power11 processor
    is exactly the same as for power10.
    
    If -mcpu=power11 is used, the macro _ARCH_PWR11 will be defined.
    
    In order to use -mcpu=power11, you will need an assembler that supports the
    -mpower11 option.
    
    In addition, this patch adds support for -mcpu=future and -mtune=future.  This
    is to allow for a way to experiment with future additions to the PowerPC
    computers that may or may not become part of the official PowerPC processor line
    up.  At the current time, no new instructions are implemented.  The tuning for
    the future processor is exactly the same as for power10.
    
    If -mcpu=future is used, the macro _ARCH_PWR_FUTURE will be defined.
    
    In order to use -mcpu=future, you will need an assembler that supports the
    -mfuture option.
    
    2024-02-21  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config.gcc (powerpc*-*-*, rs6000-*-*): Add support for power11 and
            future processors.
            * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
            _ARCH_PWR11 if -mcpu=power11 and _ARCH_PWR_FUTURE if -mcpu=future.
            * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): Add support
            for -mcpu=power11.
            (ISA_FUTURE_MASKS_SERVER): Add support for -mcpu=future.
            (POWERPC_MASKS): Add support for -mcpu=power11 and -mcpu=future.
            (power11 cpu): Add power11 cpu.
            (future cpu): Add future cpu.
            * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): New macro.
            (PROCESSOR_FUTURE): Likewise.
            * config/rs6000/rs6000-tables.opt: Regenerate.
            * config/rs6000/rs6000.cc (rs6000_machine_from_flags): If -mcpu=power11,
            emit .machine power11.  If -mcpu=future emit .machine future.
            (rs6000_opt_masks): Add support for power11 and future ISA bits.
            * config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mfuture to the assembler
            if -mcpu=future.  Pass -mpower11 to the assembler if -mcpu=power11.
            * config/rs6000/rs6000.opt (-mpower11): New internal ISA bit for
            power11 cpu.
            (-mfuture): New internal ISA bit for future cpu.
            * doc/invoke.texi (PowerPC options): Document -mcpu=future and
            -mcpu=power11.

Diff:
---
 gcc/config.gcc                      |  7 ++++---
 gcc/config/rs6000/rs6000-c.cc       |  4 ++++
 gcc/config/rs6000/rs6000-cpus.def   | 12 ++++++++++++
 gcc/config/rs6000/rs6000-opts.h     |  4 ++++
 gcc/config/rs6000/rs6000-tables.opt |  6 ++++++
 gcc/config/rs6000/rs6000.cc         |  6 ++++++
 gcc/config/rs6000/rs6000.h          |  2 ++
 gcc/config/rs6000/rs6000.opt        |  6 ++++++
 gcc/doc/invoke.texi                 |  5 +++--
 9 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index a0f9c6723083..421d2482d248 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -530,7 +530,8 @@ powerpc*-*-*)
 	extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
 	extra_headers="${extra_headers} amo.h"
 	case x$with_cpu in
-	    xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+	    xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|\
+	    xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
 		cpu_is_64bit=yes
 		;;
 	esac
@@ -5554,8 +5555,8 @@ case "${target}" in
 				eval "with_$which=405"
 				;;
 			"" | common | native \
-			| power[3456789] | power10 | power5+ | power6x \
-			| powerpc | powerpc64 | powerpc64le \
+			| power[3456789] | power1[01] | power5+ | power6x \
+			| powerpc | powerpc64 | powerpc64le | future \
 			| rs64 \
 			| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
 			| 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d373..d15bb85743c1 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
   if ((flags & OPTION_MASK_POWER10) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+  if ((flags & OPTION_MASK_POWER11) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
+  if ((flags & OPTION_MASK_FUTURE) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 276f3cdecaf1..01de96bc2498 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,14 @@
 				 | OPTION_MASK_POWER10			\
 				 | OTHER_POWER10_MASKS)
 
+/* Flags for a Power11 processor.  */
+#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER			\
+				  | OPTION_MASK_POWER11)
+
+/* Flags for a potential future processor that may or may not be made.  */
+#define ISA_FUTURE_MASKS_SERVER	(ISA_POWER11_MASKS_SERVER		\
+				 | OPTION_MASK_FUTURE)
+
 /* Flags that need to be turned off if -mno-power9-vector.  */
 #define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
 				 | OPTION_MASK_P9_MINMAX)
@@ -131,7 +139,9 @@
 				 | OPTION_MASK_FLOAT128_KEYWORD		\
 				 | OPTION_MASK_FPRND			\
 				 | OPTION_MASK_POWER10			\
+				 | OPTION_MASK_POWER11			\
 				 | OPTION_MASK_P10_FUSION		\
+				 | OPTION_MASK_FUTURE			\
 				 | OPTION_MASK_HTM			\
 				 | OPTION_MASK_ISEL			\
 				 | OPTION_MASK_MFCRF			\
@@ -263,3 +273,5 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
 	    | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
 RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 33fd0efc936f..96a72c50c459 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -70,6 +70,10 @@ enum processor_type
    PROCESSOR_TITAN
 };
 
+/* Until there are changes in instruction tuning for either power11 or a
+   possible future cpu, treat them to be like -mtune=power10.  */
+#define PROCESSOR_POWER11	PROCESSOR_POWER10
+#define PROCESSOR_FUTURE	PROCESSOR_POWER10
 
 /* Types of costly dependences.  */
 enum rs6000_dependence_cost
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 65f46709716f..f009c4e57186 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -197,3 +197,9 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
 EnumValue
 Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
 
+EnumValue
+Enum(rs6000_cpu_opt_value) String(power11) Value(57)
+
+EnumValue
+Enum(rs6000_cpu_opt_value) String(future) Value(58)
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 5d975dab9216..b071541ea3a6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5920,6 +5920,10 @@ rs6000_machine_from_flags (void)
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
 
+  if ((flags & OPTION_MASK_FUTURE) != 0)
+    return "future";
+  if ((flags & OPTION_MASK_POWER11) != 0)
+    return "power11";
   if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
     return "power10";
   if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -24476,6 +24480,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "float128",			OPTION_MASK_FLOAT128_KEYWORD,	false, true  },
   { "float128-hardware",	OPTION_MASK_FLOAT128_HW,	false, true  },
   { "fprnd",			OPTION_MASK_FPRND,		false, true  },
+  { "future",			OPTION_MASK_FUTURE,		false, false },
   { "power10",			OPTION_MASK_POWER10,		false, true  },
   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
   { "htm",			OPTION_MASK_HTM,		false, true  },
@@ -24497,6 +24502,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "power9-misc",		OPTION_MASK_P9_MISC,		false, true  },
   { "power9-vector",		OPTION_MASK_P9_VECTOR,		false, true  },
   { "power10-fusion",		OPTION_MASK_P10_FUSION,		false, true  },
+  { "power11",			OPTION_MASK_POWER11,		false, false },
   { "powerpc-gfxopt",		OPTION_MASK_PPC_GFXOPT,		false, true  },
   { "powerpc-gpopt",		OPTION_MASK_PPC_GPOPT,		false, true  },
   { "prefixed",			OPTION_MASK_PREFIXED,		false, true  },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2291fe8d3a34..f6025fbc6d67 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -107,6 +107,8 @@
    to the assembler if -mpower9-vector was also used.  */
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
+  mcpu=power11: -mpower11; \
   mcpu=power10: -mpower10; \
   mcpu=power9: -mpower9; \
   mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 5e32ee9b685d..55527c15ed4b 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -604,6 +604,12 @@ mrop-protect
 Target Var(rs6000_rop_protect) Init(0)
 Enable instructions that guard against return-oriented programming attacks.
 
+mpower11
+Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
+
+mfuture
+Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
+
 mprivileged
 Target Var(rs6000_privileged) Init(0)
 Generate code that will run in privileged state.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e18886e0ac7b..cd9eb2bb7b01 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31121,8 +31121,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
 @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
 @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
 @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
+@samp{power9}, @samp{power10}, @samp{power11},
+@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
+@samp{rs64}, @samp{future}, and @samp{native}.
 
 @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
 @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either

^ permalink raw reply	[flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work159)] Add -mcpu=power11 and -mcpu=future support.
@ 2024-02-21 18:34 Michael Meissner
  0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2024-02-21 18:34 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:714d4da4e751ec9f23b427997a15257ed9484ae4

commit 714d4da4e751ec9f23b427997a15257ed9484ae4
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Feb 21 13:31:42 2024 -0500

    Add -mcpu=power11 and -mcpu=future support.
    
    This patch adds support for -mcpu=power11 and -mtune=power11.  At the current
    time, no new instructions are implemented.  The tuning for the power11 processor
    is exactly the same as for power10.
    
    If -mcpu=power11 is used, the macro _ARCH_PWR11 will be defined.
    
    In order to use -mcpu=power11, you will need an assembler that supports the
    -mpower11 option.
    
    In addition, this patch adds support for -mcpu=future and -mtune=future.  This
    is to allow for a way to experiment with future additions to the PowerPC
    computers that may or may not become part of the official PowerPC processor line
    up.  At the current time, no new instructions are implemented.  The tuning for
    the future processor is exactly the same as for power10.
    
    If -mcpu=future is used, the macro _ARCH_PWR_FUTURE will be defined.
    
    In order to use -mcpu=future, you will need an assembler that supports the
    -mfuture option.
    
    2024-02-21  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config.gcc (powerpc*-*-*, rs6000-*-*): Add support for power11 and
            future processors.
            * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
            _ARCH_PWR11 if -mcpu=power11 and _ARCH_PWR_FUTURE if -mcpu=future.
            * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): Add support
            for -mcpu=power11.
            (ISA_FUTURE_MASKS_SERVER): Add support for -mcpu=future.
            (POWERPC_MASKS): Add support for -mcpu=power11 and -mcpu=future.
            (power11 cpu): Add power11 cpu.
            (future cpu): Add future cpu.
            * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): New macro.
            (PROCESSOR_FUTURE): Likewise.
            * config/rs6000/rs6000-tables.opt: Regenerate.
            * config/rs6000/rs6000.cc (rs6000_machine_from_flags): If -mcpu=power11,
            emit .machine power11.  If -mcpu=future emit .machine future.
            (rs6000_opt_masks): Add support for power11 and future ISA bits.
            * config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mfuture to the assembler
            if -mcpu=future.  Pass -mpower11 to the assembler if -mcpu=power11.
            * config/rs6000/rs6000.opt (-mpower11): New internal ISA bit for
            power11 cpu.
            (-mfuture): New internal ISA bit for future cpu.
            * doc/invoke.texi (PowerPC options): Document -mcpu=future and
            -mcpu=power11.

Diff:
---
 gcc/config.gcc                      |  7 ++++---
 gcc/config/rs6000/rs6000-c.cc       |  4 ++++
 gcc/config/rs6000/rs6000-cpus.def   | 13 +++++++++++++
 gcc/config/rs6000/rs6000-opts.h     |  4 ++++
 gcc/config/rs6000/rs6000-tables.opt |  6 ++++++
 gcc/config/rs6000/rs6000.cc         |  6 ++++++
 gcc/config/rs6000/rs6000.h          |  2 ++
 gcc/config/rs6000/rs6000.opt        |  6 ++++++
 gcc/doc/invoke.texi                 |  5 +++--
 9 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index a0f9c6723083..421d2482d248 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -530,7 +530,8 @@ powerpc*-*-*)
 	extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
 	extra_headers="${extra_headers} amo.h"
 	case x$with_cpu in
-	    xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+	    xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|\
+	    xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
 		cpu_is_64bit=yes
 		;;
 	esac
@@ -5554,8 +5555,8 @@ case "${target}" in
 				eval "with_$which=405"
 				;;
 			"" | common | native \
-			| power[3456789] | power10 | power5+ | power6x \
-			| powerpc | powerpc64 | powerpc64le \
+			| power[3456789] | power1[01] | power5+ | power6x \
+			| powerpc | powerpc64 | powerpc64le | future \
 			| rs64 \
 			| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
 			| 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d373..d15bb85743c1 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
   if ((flags & OPTION_MASK_POWER10) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+  if ((flags & OPTION_MASK_POWER11) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
+  if ((flags & OPTION_MASK_FUTURE) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 276f3cdecaf1..e75321ddb838 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,14 @@
 				 | OPTION_MASK_POWER10			\
 				 | OTHER_POWER10_MASKS)
 
+/* Flags for a Power11 processor.  */
+#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER			\
+				  | OPTION_MASK_POWER11)
+
+/* Flags for a potential future processor that may or may not be made.  */
+#define ISA_FUTURE_MASKS_SERVER	(ISA_POWER11_MASKS_SERVER		\
+				 | OPTION_MASK_FUTURE)
+
 /* Flags that need to be turned off if -mno-power9-vector.  */
 #define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
 				 | OPTION_MASK_P9_MINMAX)
@@ -121,6 +129,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
 #define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
+				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_CMPB			\
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_DFP			\
@@ -131,7 +140,9 @@
 				 | OPTION_MASK_FLOAT128_KEYWORD		\
 				 | OPTION_MASK_FPRND			\
 				 | OPTION_MASK_POWER10			\
+				 | OPTION_MASK_POWER11			\
 				 | OPTION_MASK_P10_FUSION		\
+				 | OPTION_MASK_FUTURE			\
 				 | OPTION_MASK_HTM			\
 				 | OPTION_MASK_ISEL			\
 				 | OPTION_MASK_MFCRF			\
@@ -263,3 +274,5 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
 	    | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
 RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 33fd0efc936f..96a72c50c459 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -70,6 +70,10 @@ enum processor_type
    PROCESSOR_TITAN
 };
 
+/* Until there are changes in instruction tuning for either power11 or a
+   possible future cpu, treat them to be like -mtune=power10.  */
+#define PROCESSOR_POWER11	PROCESSOR_POWER10
+#define PROCESSOR_FUTURE	PROCESSOR_POWER10
 
 /* Types of costly dependences.  */
 enum rs6000_dependence_cost
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 65f46709716f..f009c4e57186 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -197,3 +197,9 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
 EnumValue
 Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
 
+EnumValue
+Enum(rs6000_cpu_opt_value) String(power11) Value(57)
+
+EnumValue
+Enum(rs6000_cpu_opt_value) String(future) Value(58)
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 5d975dab9216..b071541ea3a6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5920,6 +5920,10 @@ rs6000_machine_from_flags (void)
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
 
+  if ((flags & OPTION_MASK_FUTURE) != 0)
+    return "future";
+  if ((flags & OPTION_MASK_POWER11) != 0)
+    return "power11";
   if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
     return "power10";
   if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -24476,6 +24480,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "float128",			OPTION_MASK_FLOAT128_KEYWORD,	false, true  },
   { "float128-hardware",	OPTION_MASK_FLOAT128_HW,	false, true  },
   { "fprnd",			OPTION_MASK_FPRND,		false, true  },
+  { "future",			OPTION_MASK_FUTURE,		false, false },
   { "power10",			OPTION_MASK_POWER10,		false, true  },
   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
   { "htm",			OPTION_MASK_HTM,		false, true  },
@@ -24497,6 +24502,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "power9-misc",		OPTION_MASK_P9_MISC,		false, true  },
   { "power9-vector",		OPTION_MASK_P9_VECTOR,		false, true  },
   { "power10-fusion",		OPTION_MASK_P10_FUSION,		false, true  },
+  { "power11",			OPTION_MASK_POWER11,		false, false },
   { "powerpc-gfxopt",		OPTION_MASK_PPC_GFXOPT,		false, true  },
   { "powerpc-gpopt",		OPTION_MASK_PPC_GPOPT,		false, true  },
   { "prefixed",			OPTION_MASK_PREFIXED,		false, true  },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2291fe8d3a34..f6025fbc6d67 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -107,6 +107,8 @@
    to the assembler if -mpower9-vector was also used.  */
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
+  mcpu=power11: -mpower11; \
   mcpu=power10: -mpower10; \
   mcpu=power9: -mpower9; \
   mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 5e32ee9b685d..55527c15ed4b 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -604,6 +604,12 @@ mrop-protect
 Target Var(rs6000_rop_protect) Init(0)
 Enable instructions that guard against return-oriented programming attacks.
 
+mpower11
+Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
+
+mfuture
+Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
+
 mprivileged
 Target Var(rs6000_privileged) Init(0)
 Generate code that will run in privileged state.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e18886e0ac7b..cd9eb2bb7b01 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31121,8 +31121,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
 @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
 @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
 @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
+@samp{power9}, @samp{power10}, @samp{power11},
+@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
+@samp{rs64}, @samp{future}, and @samp{native}.
 
 @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
 @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either

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2024-02-21 19:01 [gcc(refs/users/meissner/heads/work159)] Add -mcpu=power11 and -mcpu=future support Michael Meissner
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2024-02-21 18:34 Michael Meissner

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