[gcc r14-9126] Daily bump.

[gcc r14-9126] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:98004ca00e4bf7a513cf3de65d3c3d9ad373872e

commit r14-9126-g98004ca00e4bf7a513cf3de65d3c3d9ad373872e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Feb 22 00:18:58 2024 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 184 +++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |   2 +-
 gcc/analyzer/ChangeLog  |  16 ++++
 gcc/lto/ChangeLog       |   7 ++
 gcc/m2/ChangeLog        |  49 +++++++++++
 gcc/rust/ChangeLog      |  47 +++++++++++
 gcc/testsuite/ChangeLog | 213 ++++++++++++++++++++++++++++++++++++++++++++++++
 libcpp/po/ChangeLog     |   4 +
 libgcc/ChangeLog        |   7 ++
 libgomp/ChangeLog       |   5 ++
 10 files changed, 533 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9fe70cb7e490..c7709373ba2b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,187 @@
+2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
+
+	* config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
+
+2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
+	    Robin Dapp  <rdapp.gcc@gmail.com>
+
+	* config/riscv/generic-ooo.md (generic_ooo): Move reservation
+	(generic_ooo_vec_load): Ditto
+	(generic_ooo_vec_store): Ditto
+	(generic_ooo_vec_loadstore_seg): Ditto
+	(generic_ooo_vec_alu): Ditto
+	(generic_ooo_vec_fcmp): Ditto
+	(generic_ooo_vec_imul): Ditto
+	(generic_ooo_vec_fadd): Ditto
+	(generic_ooo_vec_fmul): Ditto
+	(generic_ooo_crypto): Ditto
+	(generic_ooo_perm): Ditto
+	(generic_ooo_vec_reduction): Ditto
+	(generic_ooo_vec_ordered_reduction): Ditto
+	(generic_ooo_vec_idiv): Ditto
+	(generic_ooo_vec_float_divsqrt): Ditto
+	(generic_ooo_vec_mask): Ditto
+	(generic_ooo_vec_vesetvl): Ditto
+	(generic_ooo_vec_setrm): Ditto
+	(generic_ooo_vec_readlen): Ditto
+	* config/riscv/riscv.md: Include generic-vector-ooo
+	* config/riscv/generic-vector-ooo.md: New file. To here
+
+2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
+
+	* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
+	(generic_ooo_branch): Ditto
+	* config/riscv/generic.md (generic_sfb_alu): Ditto
+	(generic_fmul_half): Ditto
+	* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
+	* config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
+	(sifive_7_popcount): Ditto
+	* config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
+	* config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
+	* config/riscv/vector.md: Change rdfrm to fmove
+	* config/riscv/zc.md: Change pushpop to load/store
+
+2024-02-21  Jonathan Wakely  <jwakely@redhat.com>
+
+	* doc/invoke.texi (Warning Options): Fix typos.
+
+2024-02-21  David Faust  <david.faust@oracle.com>
+
+	* config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
+	* config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
+	* config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
+
+2024-02-21  Martin Jambor  <mjambor@suse.cz>
+
+	PR ipa/113476
+	* ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
+	initializers in the contructor.
+	(ipa_node_params::~ipa_node_params): Release lattices as a vector.
+	* ipa-cp.h: New file.
+	* ipa-cp.cc: Include sreal.h and ipa-cp.h.
+	(ipcp_value_source): Move to ipa-cp.h.
+	(ipcp_value_base): Likewise.
+	(ipcp_value): Likewise.
+	(ipcp_lattice): Likewise.
+	(ipcp_agg_lattice): Likewise.
+	(ipcp_bits_lattice): Likewise.
+	(ipcp_vr_lattice): Likewise.
+	(ipcp_param_lattices): Likewise.
+	(ipa_get_parm_lattices): Remove assert latticess is non-NULL.
+	(ipa_value_from_jfunc): Adjust a check for empty lattices.
+	(ipa_context_from_jfunc): Likewise.
+	(ipa_agg_value_from_jfunc): Likewise.
+	(merge_agg_lats_step): Do not memset new aggregate lattices to zero.
+	(ipcp_propagate_stage): Allocate lattices in a vector as opposed to
+	just in contiguous memory.
+	(ipcp_store_vr_results): Adjust a check for empty lattices.
+	* auto-profile.cc: Include sreal.h and ipa-cp.h.
+	* cgraph.cc: Likewise.
+	* cgraphclones.cc: Likewise.
+	* cgraphunit.cc: Likewise.
+	* config/aarch64/aarch64.cc: Likewise.
+	* config/i386/i386-builtins.cc: Likewise.
+	* config/i386/i386-expand.cc: Likewise.
+	* config/i386/i386-features.cc: Likewise.
+	* config/i386/i386-options.cc: Likewise.
+	* config/i386/i386.cc: Likewise.
+	* config/rs6000/rs6000.cc: Likewise.
+	* config/s390/s390.cc: Likewise.
+	* gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
+	files to be included in gtype-desc.cc.
+	* gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
+	* ipa-devirt.cc: Likewise.
+	* ipa-fnsummary.cc: Likewise.
+	* ipa-icf.cc: Likewise.
+	* ipa-inline-analysis.cc: Likewise.
+	* ipa-inline-transform.cc: Likewise.
+	* ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
+	* ipa-modref.cc: Include sreal.h and ipa-cp.h.
+	* ipa-param-manipulation.cc: Likewise.
+	* ipa-predicate.cc: Likewise.
+	* ipa-profile.cc: Likewise.
+	* ipa-prop.cc: Likewise.
+	(ipa_node_params_t::duplicate): Assert new lattices remain empty
+	instead of setting them to NULL.
+	* ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
+	* ipa-split.cc: Likewise.
+	* ipa-sra.cc: Likewise.
+	* ipa-strub.cc: Likewise.
+	* ipa-utils.cc: Likewise.
+	* ipa.cc: Likewise.
+	* toplev.cc: Likewise.
+	* tree-ssa-ccp.cc: Likewise.
+	* tree-ssa-sccvn.cc: Likewise.
+	* tree-vrp.cc: Likewise.
+
+2024-02-21  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
+	Armv8.7-a.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
+	Use aarch64_gen_compare_zero_and_branch rather than emitting
+	a CBZ directly.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
+	Remove duplicated call.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
+	Check that each individual piece of state is shared in the same
+	way, rather than using an aggregate check for PSTATE.ZA.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
+	In the code that commits a lazy save, only zero ZA if the function
+	has ZA state.  Similarly zero ZT0 if the function has ZT0 state.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
+	directly inserting the associated sequence
+	* config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
+	...here instead.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/113995
+	* config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
+	fold the SVE allocation into the initial allocation if the
+	initial allocation includes a VG save.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/113220
+	* cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
+	contain jumps even if called after initial RTL expansion.
+	* mode-switching.cc: Include cfgbuild.h.
+	(optimize_mode_switching): Allow the sequence returned by the
+	emit hook to contain internal jumps.  Record which blocks
+	contain such jumps and split the blocks at the end.
+	* config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
+	non-debug insns when scanning the sequence.
+
+2024-02-21  Tobias Burnus  <tburnus@baylibre.com>
+
+	* config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
+	* config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
+
+2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+	* doc/invoke.texi (-mmcu): Add information about MCU specs.
+
+2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+	* doc/invoke.texi (-minrt): Clarify that main
+	must take no arguments.
+
 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
 
 	* config/avr/builtins.def: Use function prototypes of given size
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6f470e71ab94..768ab7eee3e8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240221
+20240222
diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog
index d8165bbb86d9..61b7aa1cc50d 100644
--- a/gcc/analyzer/ChangeLog
+++ b/gcc/analyzer/ChangeLog
@@ -1,3 +1,19 @@
+2024-02-21  David Malcolm  <dmalcolm@redhat.com>
+
+	PR analyzer/113999
+	* analyzer.h (get_string_cst_size): New decl.
+	* region-model-manager.cc (get_string_cst_size): New.
+	(region_model_manager::maybe_get_char_from_string_cst): Treat
+	single-byte accesses within string_cst but beyond
+	TREE_STRING_LENGTH as being 0.
+	* region-model.cc (string_cst_has_null_terminator): Likewise.
+
+2024-02-21  David Malcolm  <dmalcolm@redhat.com>
+
+	PR analyzer/113998
+	* ranges.cc (symbolic_byte_range::intersection): Handle empty ranges.
+	(selftest::test_intersects): Add test coverage for empty ranges.
+
 2024-02-19  David Malcolm  <dmalcolm@redhat.com>
 
 	PR analyzer/111289
diff --git a/gcc/lto/ChangeLog b/gcc/lto/ChangeLog
index e20654412b70..dd9310eac7c3 100644
--- a/gcc/lto/ChangeLog
+++ b/gcc/lto/ChangeLog
@@ -1,3 +1,10 @@
+2024-02-21  Martin Jambor  <mjambor@suse.cz>
+
+	PR ipa/113476
+	* lto-common.cc: Include sreal.h and ipa-cp.h.
+	* lto-partition.cc: Include ipa-cp.h, move inclusion of sreal higher.
+	* lto.cc: Include sreal.h and ipa-cp.h.
+
 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
 
 	* lto-common.cc (print_lto_report_1): Use HOST_SIZE_T_PRINT_DEC
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 6c075b2b917a..10cbe904d32c 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,52 @@
+2024-02-21  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/114026
+	* gm2-compiler/M2GenGCC.mod (Import): Remove DisplayQuadruples.
+	Remove DisplayQuadList.
+	(MixTypesBinary): Replace check with overflowCheck.
+	New variable typeChecking.
+	Use GenQuadOTypetok to retrieve typeChecking.
+	Use typeChecking to suppress error message.
+	* gm2-compiler/M2LexBuf.def (MakeVirtual2Tok): New procedure
+	function.
+	* gm2-compiler/M2LexBuf.mod (MakeVirtualTok): Improve comment.
+	(MakeVirtual2Tok): New procedure function.
+	* gm2-compiler/M2Quads.def (GetQuadOTypetok): New procedure.
+	* gm2-compiler/M2Quads.mod (QuadFrame): New field CheckType.
+	(PutQuadO): Rewrite using PutQuadOType.
+	(PutQuadOType): New procedure.
+	(GetQuadOTypetok): New procedure.
+	(BuildPseudoBy): Rewrite.
+	(BuildForToByDo): Remove type checking.
+	Add parameters e2, e2tok, BySym, bytok to
+	InitForLoopBeginRange.
+	Push the RangeId.
+	(BuildEndFor): Pop the RangeId.
+	Use GenQuadOTypetok to generate AddOp without type checking.
+	Call PutRangeForIncrement with the RangeId and IncQuad.
+	(GenQuadOtok): Rewrite using GenQuadOTypetok.
+	(GenQuadOTypetok): New procedure.
+	* gm2-compiler/M2Range.def (InitForLoopBeginRangeCheck):
+	Rename d as des, e as expr.
+	Add expr1, expr1tok, expr2, expr2tok, byconst, byconsttok
+	parameters.
+	(PutRangeForIncrement): New procedure.
+	* gm2-compiler/M2Range.mod (Import): MakeVirtual2Tok.
+	(Range): Add expr2, byconst, destok, exprtok, expr2tok,
+	incrementquad.
+	(InitRange): Initialize expr2 to NulSym.
+	Initialize byconst to NulSym.
+	Initialize tokenNo, destok, exprtok, expr2tok, byconst to
+	UnknownTokenNo.
+	Initialize incrementquad to 0.
+	(PutRangeForIncrement): New procedure.
+	(PutRangeDesExpr2): New procedure.
+	(InitForLoopBeginRangeCheck): Rewrite.
+	(ForLoopBeginTypeCompatible): New procedure function.
+	(CodeForLoopBegin): Call ForLoopBeginTypeCompatible and
+	only code the for loop assignment if all the type checks
+	succeed.
+
 2024-02-19  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	PR modula2/113889
diff --git a/gcc/rust/ChangeLog b/gcc/rust/ChangeLog
index b04423a6f639..c8049e30fff7 100644
--- a/gcc/rust/ChangeLog
+++ b/gcc/rust/ChangeLog
@@ -1,3 +1,50 @@
+2024-02-21  0xn4utilus  <gyanendrabanjare8@gmail.com>
+
+	* checks/errors/rust-ast-validation.cc (ASTValidation::visit):
+	Add variadic check on all parameters.
+
+2024-02-21  Owen Avery  <powerboat9.gamer@gmail.com>
+
+	* backend/rust-compile-pattern.cc
+	(CompilePatternLet::visit):
+	Lookup type of sub-pattern, not tuple pattern itself.
+
+2024-02-21  Marc Poulhiès  <dkm@kataplop.net>
+
+	* backend/rust-builtins.cc
+	(BuiltinsContext::register_rust_mappings): Add powi and reformat.
+	* backend/rust-builtins.h: Add missing copyright header.
+
+2024-02-21  Arthur Cohen  <arthur.cohen@embecosm.com>
+
+	* expand/rust-macro-expand.h (struct MacroExpander): Nitpick: fix
+	formatting of emitted error.
+
+2024-02-21  Owen Avery  <powerboat9.gamer@gmail.com>
+
+	* resolve/rust-ast-resolve-item.cc
+	(flatten_glob): Use Import class.
+	(flatten_rebind): Likewise.
+	(flatten_list): Likewise.
+	(flatten): Likewise.
+	(flatten_use_dec_to_paths): Likewise.
+	(flatten_use_dec_to_imports): Likewise.
+	(ResolveItem::visit): Likewise.
+	(Import::add_prefix): New.
+	(rust_flatten_nested_glob): Adjust test.
+	(rust_flatten_glob): Likewise.
+	(rust_flatten_rebind_none): Likewise.
+	(rust_flatten_rebind): Likewise.
+	(rust_flatten_rebind_nested): Likewise.
+	(rust_flatten_list): Likewise.
+	* resolve/rust-ast-resolve-item.h
+	(class Import): New.
+
+2024-02-21  Arthur Cohen  <arthur.cohen@embecosm.com>
+
+	* typecheck/rust-hir-type-check-implitem.h: Fix typo in field
+	(region_costraints -> region_constraints).
+
 2024-02-07  Kushal Pal  <kushalpal109@gmail.com>
 
 	* parse/rust-parse-impl.h (Parser::parse_trait_item):
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c9c2db7b67f5..2f1b15f46a80 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,216 @@
+2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
+
+	PR target/113249
+	* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c:
+	Rearrange and adjust asm-checker times
+	* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Ditto
+	* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Ditto
+	* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Ditto
+	* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Ditto
+	* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Ditto
+	* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c:
+	Rearrange assembly
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto
+	* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Change expected vsetvl
+
+2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
+
+	PR target/113249
+	* g++.target/riscv/rvv/base/bug-1.C: Use default scheduling
+	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: Ditto
+	* gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: Ditto
+	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: Ditto
+	* gcc.target/riscv/rvv/base/pr108185-1.c: Ditto
+	* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
+	* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
+	* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
+	* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
+	* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
+	* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
+	* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
+	* gfortran.dg/vect/vect-8.f90: Ditto
+
+2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
+
+	PR target/113742
+	* gcc.target/riscv/pr113742.c: change mcpu to mtune and add march
+
+2024-02-21  David Faust  <david.faust@oracle.com>
+
+	* gcc.target/bpf/memcpy-1.c: New test.
+	* gcc.target/bpf/memmove-1.c: New test.
+	* gcc.target/bpf/memmove-2.c: New test.
+
+2024-02-21  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/114026
+	* gm2/extensions/run/pass/callingc10.mod: New test.
+	* gm2/extensions/run/pass/callingc11.mod: New test.
+	* gm2/extensions/run/pass/callingc9.mod: New test.
+	* gm2/extensions/run/pass/strconst.def: New test.
+	* gm2/pim/fail/forloop.mod: New test.
+	* gm2/pim/pass/forloop2.mod: New test.
+
+2024-02-21  0xn4utilus  <gyanendrabanjare8@gmail.com>
+
+	* rust/compile/issue-2850.rs: New test.
+
+2024-02-21  Owen Avery  <powerboat9.gamer@gmail.com>
+
+	* rust/compile/issue-2847-b.rs: New test.
+
+2024-02-21  Marc Poulhiès  <dkm@kataplop.net>
+
+	* rust/compile/torture/intrinsics-math.rs: Adjust pow test, add
+	test for powi.
+
+2024-02-21  Arthur Cohen  <arthur.cohen@embecosm.com>
+
+	* rust/compile/rustc_const_stable.rs: New test.
+
+2024-02-21  Owen Avery  <powerboat9.gamer@gmail.com>
+
+	* rust/compile/use_2.rs: New test.
+
+2024-02-21  Arthur Cohen  <arthur.cohen@embecosm.com>
+
+	* rust/execute/torture/matches_macro.rs: New test.
+
+2024-02-21  Tamar Christina  <tamar.christina@arm.com>
+
+	* g++.target/aarch64/acle/ls64.C: Add +ls64.
+	* g++.target/aarch64/acle/ls64_lto.C: Likewise.
+	* gcc.target/aarch64/acle/ls64_lto.c: Likewise.
+	* gcc.target/aarch64/acle/pr110100.c: Likewise.
+	* gcc.target/aarch64/acle/pr110132.c: Likewise.
+	* gcc.target/aarch64/options_set_28.c: Drop check for nols64.
+	* gcc.target/aarch64/pragma_cpp_predefs_2.c: Correct header checks.
+
+2024-02-21  Tamar Christina  <tamar.christina@arm.com>
+
+	PR fortran/107071
+	* gfortran.dg/ieee/modes_1.f90: skip aarch64, arm.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sme/locally_streaming_1_ts.c: New test.
+	* gcc.target/aarch64/sme/sibcall_7_ts.c: Likewise.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sme/sibcall_9.c: New test.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sme/zt0_state_5.c (test3): Expect ZT0 rather
+	than ZA to be zeroed.
+	(test5): Remove zeroing of ZA.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sme/zt0_state_5.c (test3, test5): Expect
+	zero { za }s.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/113995
+	* gcc.target/aarch64/sme/locally_streaming_1.c: Require
+	-fno-stack-clash-protection.
+	* gcc.target/aarch64/sme/locally_streaming_1_scp.c: New test.
+
+2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/113220
+	* gcc.target/aarch64/sme/call_sm_switch_5.c: Add
+	-fno-stack-clash-protection.
+	* gcc.target/aarch64/sme/call_sm_switch_5_scp.c: New test.
+	* gcc.target/aarch64/sme/sibcall_6_scp.c: New test.
+	* gcc.target/aarch64/sme/za_state_4.c: Add
+	-fno-stack-clash-protection.
+	* gcc.target/aarch64/sme/za_state_4_scp.c: New test.
+	* gcc.target/aarch64/sme/za_state_5.c: Add
+	-fno-stack-clash-protection.
+	* gcc.target/aarch64/sme/za_state_5_scp.c: New test.
+
+2024-02-21  Ilya Leoshkevich  <iii@linux.ibm.com>
+
+	* gcc.target/s390/zvector/autovec-double-signaling-eq.c:
+	Preserve exceptions.
+	* gcc.target/s390/zvector/autovec-float-signaling-eq.c:
+	Likewise.
+
+2024-02-21  David Malcolm  <dmalcolm@redhat.com>
+
+	PR analyzer/113999
+	* c-c++-common/analyzer/strlen-pr113999.c: New test.
+	* gcc.dg/analyzer/strlen-1.c: More test coverage.
+
+2024-02-21  David Malcolm  <dmalcolm@redhat.com>
+
+	PR analyzer/113998
+	* c-c++-common/analyzer/overlapping-buffers-pr113998.c: New test.
+
 2024-02-20  Peter Hill  <peter.hill@york.ac.uk>
 
 	PR fortran/105658
diff --git a/libcpp/po/ChangeLog b/libcpp/po/ChangeLog
index 1e0175dcb202..bfaa057eaead 100644
--- a/libcpp/po/ChangeLog
+++ b/libcpp/po/ChangeLog
@@ -1,3 +1,7 @@
+2024-02-21  Joseph Myers  <josmyers@redhat.com>
+
+	* de.po: Update.
+
 2024-02-20  Joseph Myers  <josmyers@redhat.com>
 
 	* sv.po: Update.
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index dab82198daa2..6b19e12fb4b2 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,10 @@
+2024-02-21  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* config/aarch64/heap-trampoline.c
+	(aarch64_trampoline_insns): Arrange to encode instructions as a
+	byte array so that the order is independent of memory byte order.
+	(struct aarch64_trampoline): Likewise.
+
 2024-02-20  Iain Sandoe  <iain@sandoe.co.uk>
 
 	PR target/113971
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 4be1459e3044..88f06188f424 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,8 @@
+2024-02-21  Tobias Burnus  <tburnus@baylibre.com>
+
+	* libgomp.texi (OpenMP Context Selectors): Add 'nvptx64' as additional
+	'arch' value for nvptx.
+
 2024-02-15  Kwok Cheung Yeung  <kcyeung@baylibre.com>
 
 	* libgomp.texi (OpenMP 5.1): Mark indirect call support as fully