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* [gcc(refs/users/meissner/heads/work160-test)] Apply patches 1-3 from work160 branch
@ 2024-02-27 5:04 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2024-02-27 5:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:86af7575d9916b9c810fcf421e6a47a4e0623789
commit 86af7575d9916b9c810fcf421e6a47a4e0623789
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Feb 27 00:04:05 2024 -0500
Apply patches 1-3 from work160 branch
Diff:
---
gcc/ChangeLog.test | 115 +++++++++++++++++++++++++++
gcc/config.gcc | 7 +-
gcc/config/rs6000/aix71.h | 2 +
gcc/config/rs6000/aix72.h | 2 +
gcc/config/rs6000/aix73.h | 2 +
gcc/config/rs6000/driver-rs6000.cc | 2 +
gcc/config/rs6000/ppc-auxv.h | 3 +-
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 4 +
gcc/config/rs6000/rs6000-cpus.def | 14 ++++
gcc/config/rs6000/rs6000-opts.h | 4 +
gcc/config/rs6000/rs6000-tables.opt | 6 ++
gcc/config/rs6000/rs6000.cc | 6 ++
gcc/config/rs6000/rs6000.h | 2 +
gcc/config/rs6000/rs6000.opt | 6 ++
gcc/doc/invoke.texi | 5 +-
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 +++++
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 +++
gcc/testsuite/lib/target-supports.exp | 17 ++++
20 files changed, 235 insertions(+), 6 deletions(-)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 247072bdc46..6e72d4a246d 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,5 +1,120 @@
+==================== Branch work160-test, patch #3 from work160 branch ====================
+
+Use vector pair load/store for memcpy with -mcpu=future
+
+In the development for the power10 processor, GCC did not enable using the load
+vector pair and store vector pair instructions when optimizing things like
+memory copy. This patch enables using those instructions if -mcpu=future is
+used.
+
+2024-02-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using
+ load vector pair and store vector pair instructions for memory copy
+ operations.
+ (POWERPC_MASKS): Make the bit for enabling using load vector pair and
+ store vector pair operations set and reset when the PowerPC processor is
+ changed.
+
+==================== Branch work160-test, patch #2 from work160 branch ====================
+
+Add power11 aux vector and tests.
+
+This patch adds the support for using __builtin_cpu_is ("power11").
+
+This patch also adds support for the gcc driver program to detect when it is
+running on a power11 system and transforming -mcpu=native into -mcpu=power11.
+
+This patch adds a few simple tests for power11 support, assuming the assembler
+supports the -mpower11 option.
+
+2024-02-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/driver-rs6000.c (asm_names): Add power11 support.
+ * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Remove comment saying
+ this is not yet official.
+ (PPC_PLATFORM_POWER11): Add power11 support.
+ * config/rs6000/rs6000-builtin.cc (cpu_is_info): Likewise.
+
+gcc/testsuite/
+
+ * lib/target-support.exp (check_effective_target_power11_ok): Add
+ power11 support.
+ * gcc.target/powerpc/power11-1.c: New test.
+ * gcc.target/powerpc/power11-2.c: Likewise.
+ * gcc.target/powerpc/power11-3.c: Likewise.
+
+==================== Branch work160-test, patch #1 from work160 branch ====================
+
+Add -mcpu=power11 and -mcpu=future support.
+
+This patch adds support for -mcpu=power11 and -mtune=power11. At the current
+time, no new instructions are implemented. The tuning for the power11 processor
+is exactly the same as for power10.
+
+If -mcpu=power11 is used, the macro _ARCH_PWR11 will be defined.
+
+In order to use -mcpu=power11, you will need an assembler that supports the
+-mpower11 option.
+
+In addition, this patch adds support for -mcpu=future and -mtune=future. This
+is to allow for a way to experiment with future additions to the PowerPC
+computers that may or may not become part of the official PowerPC processor line
+up. At the current time, no new instructions are implemented. The tuning for
+the future processor is exactly the same as for power10.
+
+If -mcpu=future is used, the macro _ARCH_PWR_FUTURE will be defined.
+
+In order to use -mcpu=future, you will need an assembler that supports the
+-mfuture option.
+
+2024-02-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config.gcc (powerpc*-*-*, rs6000-*-*): Add support for power11 and
+ future processors.
+ * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+ _ARCH_PWR11 if -mcpu=power11 and _ARCH_PWR_FUTURE if -mcpu=future.
+ * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11
+ and -mcpu=future.
+ * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): Add support
+ for -mcpu=power11.
+ (ISA_FUTURE_MASKS_SERVER): Add support for -mcpu=future.
+ (POWERPC_MASKS): Add support for -mcpu=power11 and -mcpu=future.
+ (power11 cpu): Add power11 cpu.
+ (future cpu): Add future cpu.
+ * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): New macro.
+ (PROCESSOR_FUTURE): Likewise.
+ * config/rs6000/rs6000-tables.opt: Regenerate.
+ * config/rs6000/rs6000.cc (rs6000_machine_from_flags): If -mcpu=power11,
+ emit .machine power11. If -mcpu=future emit .machine future.
+ (rs6000_opt_masks): Add support for power11 and future ISA bits.
+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mfuture to the assembler
+ if -mcpu=future. Pass -mpower11 to the assembler if -mcpu=power11.
+ * config/rs6000/rs6000.opt (-mpower11): New internal ISA bit for
+ power11 cpu.
+ (-mfuture): New internal ISA bit for future cpu.
+ * doc/invoke.texi (PowerPC options): Document -mcpu=future and
+ -mcpu=power11.
+
==================== Branch work160-test, baseline ====================
+Add ChangeLog.test and update REVISION.
+
+2024-02-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * ChangeLog.test: New file for branch.
+ * REVISION: Update.
+
2024-02-26 Michael Meissner <meissner@linux.ibm.com>
Clone branch
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2e35a112040..977d0cc5373 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,7 +531,8 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|\
+ xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5555,8 +5556,8 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
- | powerpc | powerpc64 | powerpc64le \
+ | power[3456789] | power1[01] | power5+ | power6x \
+ | powerpc | powerpc64 | powerpc64le | future \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
| 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,8 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index c43974f577a..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,8 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index b1572bde81f..2bd6b4bb3c4 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,8 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc
index 3ebbaa42622..f4900724b98 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -451,6 +451,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
+ { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64", "-mppc" },
{ "603", "-m603" },
@@ -479,6 +480,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpower8" },
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
+ { "power11", "-mpower11" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
diff --git a/gcc/config/rs6000/ppc-auxv.h b/gcc/config/rs6000/ppc-auxv.h
index 364bba427d1..4e8636443f9 100644
--- a/gcc/config/rs6000/ppc-auxv.h
+++ b/gcc/config/rs6000/ppc-auxv.h
@@ -47,9 +47,10 @@
#define PPC_PLATFORM_PPC476 12
#define PPC_PLATFORM_POWER8 13
#define PPC_PLATFORM_POWER9 14
+#define PPC_PLATFORM_POWER10 15
/* This is not yet official. */
-#define PPC_PLATFORM_POWER10 15
+#define PPC_PLATFORM_POWER11 16
/* AT_HWCAP bits. These must match the values defined in the Linux kernel. */
#define PPC_FEATURE_32 0x80000000
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 6698274031b..f3ba1eccdbd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2493,6 +2493,7 @@ static const struct
const char *cpu;
unsigned int cpuid;
} cpu_is_info[] = {
+ { "power11", PPC_PLATFORM_POWER11 },
{ "power10", PPC_PLATFORM_POWER10 },
{ "power9", PPC_PLATFORM_POWER9 },
{ "power8", PPC_PLATFORM_POWER8 },
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d37..d15bb85743c 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+ if ((flags & OPTION_MASK_POWER11) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
+ if ((flags & OPTION_MASK_FUTURE) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 28249600318..8da1d560e49 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,15 @@
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
+/* Flags for a Power11 processor. */
+#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_POWER11)
+
+/* Flags for a potential future processor that may or may not be made. */
+#define ISA_FUTURE_MASKS_SERVER (ISA_POWER11_MASKS_SERVER \
+ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
+ | OPTION_MASK_FUTURE)
+
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -115,6 +124,7 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
+ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
@@ -125,7 +135,9 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
| OPTION_MASK_POWER10 \
+ | OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
+ | OPTION_MASK_FUTURE \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
@@ -257,3 +269,5 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 33fd0efc936..96a72c50c45 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -70,6 +70,10 @@ enum processor_type
PROCESSOR_TITAN
};
+/* Until there are changes in instruction tuning for either power11 or a
+ possible future cpu, treat them to be like -mtune=power10. */
+#define PROCESSOR_POWER11 PROCESSOR_POWER10
+#define PROCESSOR_FUTURE PROCESSOR_POWER10
/* Types of costly dependences. */
enum rs6000_dependence_cost
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 65f46709716..f009c4e5718 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -197,3 +197,9 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
EnumValue
Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
+EnumValue
+Enum(rs6000_cpu_opt_value) String(power11) Value(57)
+
+EnumValue
+Enum(rs6000_cpu_opt_value) String(future) Value(58)
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6ba9df4f02e..e3ca4e799e4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5880,6 +5880,10 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
+ if ((flags & OPTION_MASK_FUTURE) != 0)
+ return "future";
+ if ((flags & OPTION_MASK_POWER11) != 0)
+ return "power11";
if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
return "power10";
if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -24436,6 +24440,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
+ { "future", OPTION_MASK_FUTURE, false, false },
{ "power10", OPTION_MASK_POWER10, false, true },
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
@@ -24457,6 +24462,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
+ { "power11", OPTION_MASK_POWER11, false, false },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "prefixed", OPTION_MASK_PREFIXED, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 68bc45d65ba..79ce1a8cbf1 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -106,6 +106,8 @@
you make changes here, make them also there. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpower11; \
mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
mcpu=power8|mcpu=powerpc64le: -mpower8; \
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 83197681b66..8e46b8fbabb 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -604,6 +604,12 @@ mrop-protect
Target Var(rs6000_rop_protect) Init(0)
Enable instructions that guard against return-oriented programming attacks.
+mpower11
+Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
+
+mfuture
+Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
+
mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4f4ca2b7672..866aa36b5f7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31132,8 +31132,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
+@samp{power9}, @samp{power10}, @samp{power11},
+@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
+@samp{rs64}, @samp{future}, and @samp{native}.
@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 00000000000..6a2e802eedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 00000000000..7b9904c1d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 00000000000..9b2d643cc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 4138cc9a662..e23d3ec8b3c 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7104,6 +7104,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+ if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+ } else {
+ return 0
+ }
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
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