[gcc(refs/users/meissner/heads/work161)] Update ChangeLog.*

[gcc(refs/users/meissner/heads/work161)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:5fe3ea5ead0f5d4452c42105234975a028455525

commit 5fe3ea5ead0f5d4452c42105234975a028455525
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Feb 29 13:24:29 2024 -0500

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 5da583ba1e7..f2143098999 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,60 @@
+==================== Branch work161, patch #3 ====================
+
+PR target/112886, Add %S<n> to print_operand for vector pair support.
+
+In looking at support for load vector pair and store vector pair for the
+PowerPC in GCC, I noticed that we were missing a print_operand output modifier
+if you are dealing with vector pairs to print the 2nd register in the vector
+pair.
+
+If the instruction inside of the asm used the Altivec encoding, then we could
+use the %L<n> modifier:
+
+	__vector_pair *p, *q, *r;
+	// ...
+	__asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2"
+		 : "=v" (*p)
+		 : "v" (*q), "v" (*r));
+
+Likewise if we know the value to be in a tradiational FPR register, %L<n> will
+work for instructions that use the VSX encoding:
+
+	__vector_pair *p, *q, *r;
+	// ...
+	__asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2"
+		 : "=f" (*p)
+		 : "f" (*q), "f" (*r));
+
+But if have a value that is in a traditional Altivec register, and the
+instruction uses the VSX encoding, %L<n> will a value between 0 and 31, when it
+should give a value between 32 and 63.
+
+This patch adds %S<n> that acts like %x<n>, except that it adds 1 to the
+register number.
+
+This is version 2 of the patch.  The only difference is I made the test case
+simpler to read.
+
+I have tested this on power10 and power9 little endian systems and on a power9
+big endian system.  There were no regressions in the patch.  Can I apply it to
+the trunk?
+
+It would be nice if I could apply it to the open branches.  Can I backport it
+after a burn-in period?
+
+2024-02-29  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/112886
+	* config/rs6000/rs6000.cc (print_operand): Add %S<n> output modifier.
+	* doc/md.texi (Modifiers): Mention %S can be used like %x.
+
+gcc/testsuite/
+
+	PR target/112886
+	* /gcc.target/powerpc/pr112886.c: New test.
+
 ==================== Branch work161, patch #2 ====================
 
 Add -mcpu=future support.

[gcc(refs/users/meissner/heads/work161)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:7f001ef8b73215f2d9829a9f3cad6169833dbb65

commit 7f001ef8b73215f2d9829a9f3cad6169833dbb65
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Feb 29 02:12:07 2024 -0500

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 120 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 119 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e0b6d2adb63..5da583ba1e7 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,6 +1,124 @@
+==================== Branch work161, patch #2 ====================
+
+Add -mcpu=future support.
+
+This patch adds support for -mcpu=future.  At the current time, no new
+instructions are implemented.  The tuning for the future processor is exactly
+the same as for power10.
+
+If -mcpu=future is used, the macro _ARCH_PWR_FUTURE will be defined.
+
+In order to use -mcpu=future, you will need an assembler that supports the
+-mfuture option.
+
+2024-02-29  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (powerpc*-*-*, rs6000-*-*): Add support for a potential
+	future processor.
+	* config/rs6000/aix71.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR_FUTURE if -mcpu=future.
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New macro.
+	(POWERPC_MASKS): Add support for -mcpu=future.
+	(future cpu): Add future cpu.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New macro.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_machine_from_flags): If -mcpu=future,
+	emit .machine future.
+	(rs6000_opt_masks): Add support for the future ISA bits.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for the future
+	processor.
+	* config/rs6000/rs6000.opt (-mfuture): New internal ISA bit for a
+	potential future cpu.
+	* doc/invoke.texi (PowerPC options): Document -mcpu=future.
+
+==================== Branch work161, patch #1 ====================
+
+Add -mcpu=power11 support.
+
+This patch adds support for -mcpu=power11.  At the current time, no new
+instructions are implemented.  The tuning for the power11 processor is exactly
+the same as for power10.
+
+If -mcpu=power11 is used, the macro _ARCH_PWR11 will be defined.
+
+In order to use -mcpu=power11, you will need an assembler that supports the
+-mpower11 option.
+
+2024-02-29  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (powerpc*-*-*, rs6000-*-*): Add support for the power11
+	processor.
+	* config/rs6000/aix71.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/driver-rs6000.c (asm_names): Likewise.
+	* config/rs6000/rs6000-builtin.cc (cpu_is_info): Likewise.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR11 if -mcpu=power11.
+	* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New macro.
+	(POWERPC_MASKS): Add support for -mcpu=power11.
+	(power11 cpu): Add power11 cpu.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): New macro.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_machine_from_flags): If -mcpu=power11,
+	emit .machine power11.
+	(rs6000_opt_masks): Add support for the power11 ISA bits.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for the power11
+	processor.
+	* config/rs6000/rs6000.opt (-mpower11): New internal ISA bit for
+	power11 cpu.
+	* doc/invoke.texi (PowerPC options): Document -mcpu=power11.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/power11-1.c: New test.
+	* gcc.target/powerpc/power11-2.c: Likewise.
+	* gcc.target/powerpc/power11-3.c: Likewise.
+	* lib/target-support.exp (check_effective_target_power11_ok): Add
+	power11 support.
+
 ==================== Branch work161, baseline ====================
 
+Add ChangeLog.meissner and REVISION.
+
+2024-02-28  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* REVISION: New file for branch.
+	* ChangeLog.meissner: New file.
+
+gcc/c-family/
+
+	* ChangeLog.meissner: New file.
+
+gcc/c/
+
+	* ChangeLog.meissner: New file.
+
+gcc/cp/
+
+	* ChangeLog.meissner: New file.
+
+gcc/fortran/
+
+	* ChangeLog.meissner: New file.
+
+gcc/testsuite/
+
+	* ChangeLog.meissner: New file.
+
+libgcc/
+
+	* ChangeLog.meissner: New file.
+
 2024-02-28   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
-