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* [gcc(refs/users/meissner/heads/work164-vpair)] Revert all changes
@ 2024-04-09 4:43 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2024-04-09 4:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9a6e5ecfb5ac36496f700ee14b6aeed59de991a4
commit 9a6e5ecfb5ac36496f700ee14b6aeed59de991a4
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 9 00:43:54 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/mma.md | 19 ++++++-------------
gcc/config/rs6000/rs6000-cpus.def | 8 ++------
gcc/config/rs6000/rs6000.cc | 30 ++----------------------------
gcc/config/rs6000/rs6000.md | 10 +---------
gcc/config/rs6000/rs6000.opt | 8 --------
5 files changed, 11 insertions(+), 64 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 6a7d8a836db..04e2d0066df 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -292,34 +292,27 @@
gcc_assert (false);
})
-;; If the user used -mno-store-vector-pair or -mno-load-vector pair, use an
-;; alternative that does not allow indexed addresses so we can split the load
-;; or store.
(define_insn_and_split "*movoo"
- [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,wa,ZwO,QwO,wa")
- (match_operand:OO 1 "input_operand" "ZwO,QwO,wa,wa,wa"))]
+ [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO,wa")
+ (match_operand:OO 1 "input_operand" "ZwO,wa,wa"))]
"TARGET_MMA
&& (gpc_reg_operand (operands[0], OOmode)
|| gpc_reg_operand (operands[1], OOmode))"
"@
lxvp%X1 %x0,%1
- #
stxvp%X0 %x1,%0
- #
#"
"&& reload_completed
- && ((MEM_P (operands[0]) && !TARGET_STORE_VECTOR_PAIR)
- || (MEM_P (operands[1]) && !TARGET_LOAD_VECTOR_PAIR)
- || (!MEM_P (operands[0]) && !MEM_P (operands[1])))"
+ && (!MEM_P (operands[0]) && !MEM_P (operands[1]))"
[(const_int 0)]
{
rs6000_split_multireg_move (operands[0], operands[1]);
DONE;
}
- [(set_attr "type" "vecload,vecload,vecstore,vecstore,veclogical")
+ [(set_attr "type" "vecload,vecstore,veclogical")
(set_attr "size" "256")
- (set_attr "length" "*,8,*,8,8")
- (set_attr "isa" "lxvp,*,stxvp,*,*")])
+ (set_attr "length" "*,*,8")])
+
\f
;; Vector quad support. XOmode can only live in FPRs.
(define_expand "movxo"
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 6e0b2449b18..47365534af8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -77,12 +77,10 @@
/* Flags that need to be turned off if -mno-power10. */
/* We comment out PCREL_OPT here to disable it by default because SPEC2017
performance was degraded by it. */
-#define OTHER_POWER10_MASKS (OPTION_MASK_LOAD_VECTOR_PAIR \
- | OPTION_MASK_MMA \
+#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
| OPTION_MASK_PCREL \
/* | OPTION_MASK_PCREL_OPT */ \
- | OPTION_MASK_PREFIXED \
- | OPTION_MASK_STORE_VECTOR_PAIR)
+ | OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
@@ -133,7 +131,6 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
| OPTION_MASK_FUTURE \
- | OPTION_MASK_LOAD_VECTOR_PAIR \
| OPTION_MASK_POWER10 \
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
@@ -161,7 +158,6 @@
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
- | OPTION_MASK_STORE_VECTOR_PAIR \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_VSX)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index da7cfa3c09e..2921e72aea8 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2722,9 +2722,7 @@ rs6000_setup_reg_addr_masks (void)
/* Vector pairs can do both indexed and offset loads if the
instructions are enabled, otherwise they can only do offset loads
since it will be broken into two vector moves. Vector quads can
- only do offset loads. If the user restricted generation of either
- of the LXVP or STXVP instructions, do not allow indexed mode so
- that we can split the load/store. */
+ only do offset loads. */
else if ((addr_mask != 0) && TARGET_MMA
&& (m2 == OOmode || m2 == XOmode))
{
@@ -2732,9 +2730,7 @@ rs6000_setup_reg_addr_masks (void)
if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
{
addr_mask |= RELOAD_REG_QUAD_OFFSET;
- if (m2 == OOmode
- && TARGET_LOAD_VECTOR_PAIR
- && TARGET_STORE_VECTOR_PAIR)
+ if (m2 == OOmode)
addr_mask |= RELOAD_REG_INDEXED;
}
}
@@ -4379,26 +4375,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_MMA;
}
- /* Warn if -m-load-vector-pair or -m-store-vector-pair are used and MMA is
- not set. */
- if (!TARGET_MMA && TARGET_LOAD_VECTOR_PAIR)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_LOAD_VECTOR_PAIR) != 0)
- warning (0, "%qs should not be used unless you use %qs",
- "-mload-vector-pair", "-mmma");
-
- rs6000_isa_flags &= ~OPTION_MASK_LOAD_VECTOR_PAIR;
- }
-
- if (!TARGET_MMA && TARGET_STORE_VECTOR_PAIR)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_STORE_VECTOR_PAIR) != 0)
- warning (0, "%qs should not be used unless you use %qs",
- "-mstore-vector-pair", "-mmma");
-
- rs6000_isa_flags &= OPTION_MASK_STORE_VECTOR_PAIR;
- }
-
/* Enable power10 fusion if we are tuning for power10, even if we aren't
generating power10 instructions. */
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
@@ -24494,7 +24470,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
- { "load-vector-pair", OPTION_MASK_LOAD_VECTOR_PAIR, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
@@ -24519,7 +24494,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
{ "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
- { "store-vector-pair", OPTION_MASK_STORE_VECTOR_PAIR, false, true },
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 66f35b4dbe9..abc809448ad 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -355,7 +355,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,lxvp,stxvp"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -403,14 +403,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "lxvp")
- (match_test "TARGET_LOAD_VECTOR_PAIR"))
- (const_int 1)
-
- (and (eq_attr "isa" "stxvp")
- (match_test "TARGET_STORE_VECTOR_PAIR"))
- (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 86a53fd3023..621ebd65a88 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -603,14 +603,6 @@ mmma
Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.
-mload-vector-pair
-Target Undocumented Mask(LOAD_VECTOR_PAIR) Var(rs6000_isa_flags)
-Generate (do not generate) load vector pair instructions.
-
-mstore-vector-pair
-Target Undocumented Mask(STORE_VECTOR_PAIR) Var(rs6000_isa_flags)
-Generate (do not generate) store vector pair instructions.
-
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
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