[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:7258b3c700907ddf947ab5e85478456783138ada

commit 7258b3c700907ddf947ab5e85478456783138ada
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 10 11:36:10 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 56a8be15cb1..7aa77ab7504 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,60 @@
+==================== Branch work164-bugs, patch #204 ====================
+
+PR target/112886, Add %S<n> to print_operand for vector pair support.
+
+In looking at support for load vector pair and store vector pair for the
+PowerPC in GCC, I noticed that we were missing a print_operand output modifier
+if you are dealing with vector pairs to print the 2nd register in the vector
+pair.
+
+If the instruction inside of the asm used the Altivec encoding, then we could
+use the %L<n> modifier:
+
+	__vector_pair *p, *q, *r;
+	// ...
+	__asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2"
+		 : "=v" (*p)
+		 : "v" (*q), "v" (*r));
+
+Likewise if we know the value to be in a tradiational FPR register, %L<n> will
+work for instructions that use the VSX encoding:
+
+	__vector_pair *p, *q, *r;
+	// ...
+	__asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2"
+		 : "=f" (*p)
+		 : "f" (*q), "f" (*r));
+
+But if have a value that is in a traditional Altivec register, and the
+instruction uses the VSX encoding, %L<n> will a value between 0 and 31, when it
+should give a value between 32 and 63.
+
+This patch adds %S<n> that acts like %x<n>, except that it adds 1 to the
+register number.
+
+This is version 2 of the patch.  The only difference is I made the test case
+simpler to read.
+
+I have tested this on power10 and power9 little endian systems and on a power9
+big endian system.  There were no regressions in the patch.  Can I apply it to
+the trunk?
+
+It would be nice if I could apply it to the open branches.  Can I backport it
+after a burn-in period?
+
+2024-04-10  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/112886
+	* config/rs6000/rs6000.cc (print_operand): Add %S<n> output modifier.
+	* doc/md.texi (Modifiers): Mention %S can be used like %x.
+
+gcc/testsuite/
+
+	PR target/112886
+	* /gcc.target/powerpc/pr112886.c: New test.
+
 ==================== Branch work164-bugs, patch #203 ====================
 
 Add power10 ori/oris and xori/xoris fusion support.

[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:87d20d149ee92ba3ba0415299eae6dce12482bec

commit 87d20d149ee92ba3ba0415299eae6dce12482bec
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 12 14:39:02 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 1b5fe755ae5..ed1739ca4df 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -7,12 +7,17 @@ Simplify converting between SImode and SF/DFmode.
 gcc/
 
 	PR target/90822
-	* gcc/config/rs6000.md (floatsidf2): If SImode can live in the floating
-	point registers, directly issue a conversion to DImode and do the
-	floating point conversion.
+	* gcc/config/rs6000.md (uns code attribute): Add sign_extend and
+	zero_extend.
+	(floatsidf2): If SImode can live in the floating point registers,
+	directly issue a conversion to DImode and do the floating point
+	conversion during expansion instead of using an UNSPEC.
 	(floatunssisf2): Likewise.
 	(floatunssidf2): Likewise.
 	(floatsisf2): Likewise.
+	* gcc/config/rs6000/vsx.md (vsx_extract_si_<uns>float_df): Adjust
+	combiner to expect sign/zero extend of SImode to DImode in optimizing
+	V4SI extracts.
 
 ==================== Branch work164-bugs, patch #205 ====================

[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:6ae9d9f24734d61f20bc06a96cecd6c02f77d5d7

commit 6ae9d9f24734d61f20bc06a96cecd6c02f77d5d7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 12 03:30:47 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index b159df68df3..1b5fe755ae5 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -2,7 +2,7 @@
 
 Simplify converting between SImode and SF/DFmode.
 
-2024-04-11  Michael Meissner  <meissner@linux.ibm.com>
+2024-04-12  Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/

[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:be19bba37f34c8993f27fcb9b65b63b30fa3b5fc

commit be19bba37f34c8993f27fcb9b65b63b30fa3b5fc
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 10 12:09:56 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 7aa77ab7504..c21696078f1 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,38 @@
+==================== Branch work164-bugs, patch #205 ====================
+
+Improve 64->128 bit zero extension on PowerPC (PR target/108958)
+
+If we are converting an unsigned DImode to a TImode value, and the TImode value
+will go in a vector register, GCC currently does the DImode to TImode conversion
+in GPR registers, and then moves the value to the vector register via a mtvsrdd
+instruction.
+
+This patch adds a new zero_extendditi2 insn which optimizes moving a GPR to a
+vector register using the mtvsrdd instruction with RA=0, and using lxvrdx to
+load a 64-bit value into the bottom 64-bits of the vector register.
+
+I have tested this patch on the following systems and there was no degration.
+Can I check it into the trunk branch?
+
+    *	Power10, LE, --with-cpu=power10, IBM 128-bit long double
+    *	Power9,  LE, --with-cpu=power9,  IBM 128-bit long double
+    *	Power9,  LE, --with-cpu=power9,  IEEE 128-bit long double
+    *   Power9,  LE, --with-cpu=power9,  64-bit default long double
+    *	Power9,  BE, --with-cpu=power9,  IBM 128-bit long double
+    *	Power8,  BE, --with-cpu=power8,  IBM 128-bit long double
+
+2024-04-10  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/108958
+	* gcc/config/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+	PR target/108958
+	* gcc.target/powerpc/pr108958.c: New test.
+
 ==================== Branch work164-bugs, patch #204 ====================
 
 PR target/112886, Add %S<n> to print_operand for vector pair support.

[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:b625c0e07fea0aaa8ce9350d2f1d3aa00cb47da0

commit b625c0e07fea0aaa8ce9350d2f1d3aa00cb47da0
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 9 17:43:41 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 7d8469fc090..56a8be15cb1 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,16 +1,23 @@
-==================== Branch work164-bugs, patch #202 ====================
+==================== Branch work164-bugs, patch #203 ====================
 
-Make sure wide immediate fusion does not generate illegal instructions.
+Add power10 ori/oris and xori/xoris fusion support.
 
 2024-04-09  Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
 	* config/rs6000/fusion.md: Regenerate.
-	* config/rs6000/genfusion.md (gen_wide_immediate): Fix code.
+	* config/rs6000/genfusion.md (gen_wide_immediate): Add wide immediate
+	fusion patterns.
 	* config/rs6000/predicates.md (u32bit_cint_2_insns_operand): New predicate.
+	* config/rs6000/rs6000.md (IORXOR_OP): New code attribute.
+	(ior, xor splitter): Do not split ior/xor patterns that could be fused
+	on power10.
+
+Make sure wide immediate fusion does not generate illegal instructions.
 
-==================== Branch work164-bugs, patch #201 ====================
+==================== Branch work164-bugs, patch #202 was reverted ====================
+==================== Branch work164-bugs, patch #201 was reverted ====================
 
 Add power10 ori/oris and xori/xoris fusion support.

[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:5ca445c7dea2add58d7ca7992b3f98d304bb3dda

commit 5ca445c7dea2add58d7ca7992b3f98d304bb3dda
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 9 15:39:24 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 9c793434348..7d8469fc090 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,15 @@
+==================== Branch work164-bugs, patch #202 ====================
+
+Make sure wide immediate fusion does not generate illegal instructions.
+
+2024-04-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/fusion.md: Regenerate.
+	* config/rs6000/genfusion.md (gen_wide_immediate): Fix code.
+	* config/rs6000/predicates.md (u32bit_cint_2_insns_operand): New predicate.
+
 ==================== Branch work164-bugs, patch #201 ====================
 
 Add power10 ori/oris and xori/xoris fusion support.

[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:d332fba26fbf1202b38fe1d51002abbcbdd4bcbf

commit d332fba26fbf1202b38fe1d51002abbcbdd4bcbf
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 9 00:34:39 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 176 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 175 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 4291f519935..9c793434348 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,6 +1,180 @@
+==================== Branch work164-bugs, patch #201 ====================
+
+Add power10 ori/oris and xori/xoris fusion support.
+
+2024-04-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/fusion.md: Regenerate.
+	* config/rs6000/genfusion.md (gen_wide_immediate): Add wide immediate
+	fusion patterns.
+	* config/rs6000/rs6000.md (IORXOR_OP): New code attribute.
+	(ior, xor splitter): Do not split ior/xor patterns that could be fused
+	on power10.
+
+==================== Branch work164-bugs, patch #200 ====================
+
+Add power10 wide immediate fusion
+
+2024-04-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/108018
+	* config/rs6000/rs6000.md (tocref<mode>_p10_fusion): New insn.
+	(tocref<mode>): Don't allow tocrev<mode> if tocref<mode>_p10_fusion
+	would be used.
+
+==================== Branch work164-bugs, patch #10 from work164 ====================
+
+Add -mcpu=future support.
+
+This patch adds the future option to the -mcpu= and -mtune= switches.
+
+This patch treats the future like a power11 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine future" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
+
+This patch allows GCC to be configured with the --with-cpu=future and
+--with-tune=future options.
+
+This patch passes -mfuture to the assembler if the user uses -mcpu=future.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+	* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+	* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR_FUTURE if -mcpu=future.
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define.
+	(POWERPC_MASKS): Add future isa bit.
+	(power11 cpu): Add future definition.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor.
+	* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future
+	support.
+	(rs6000_machine_from_flags): Likewise.
+	(rs6000_reassociation_width): Likewise.
+	(rs6000_adjust_cost): Likewise.
+	(rs6000_issue_rate): Likewise.
+	(rs6000_sched_reorder): Likewise.
+	(rs6000_sched_reorder2): Likewise.
+	(rs6000_register_move_cost): Likewise.
+	(rs6000_opt_masks): Likewise.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/rs6000.md (cpu attribute): Add future.
+	* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag.
+	* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future.
+
+==================== Branch work164-bugs, patch #3 from work164 ====================
+
+Add -mcpu=power11 tests.
+
+This patch adds some simple tests for -mcpu=power11 support.  In order to run
+these tests, you need an assembler that supports the appropriate option for
+supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX).
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/power11-1.c: New test.
+	* gcc.target/powerpc/power11-2.c: Likewise.
+	* gcc.target/powerpc/power11-3.c: Likewise.
+	* lib/target-supports.exp (check_effective_target_power11_ok): Add new
+	effective target.
+
+==================== Branch work164-bugs, patch #2 from work164 ====================
+
+Add -mcpu=power11 tuning support.
+
+This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/power10.md (all reservations): Add power11 as an
+	alternative to power10.
+
+==================== Branch work164-bugs, patch #1 from work164 ====================
+
+Add -mcpu=power11 support.
+
+This patch adds the power11 option to the -mcpu= and -mtune= switches.
+
+This patch treats the power11 like a power10 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine power11" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
+
+This patch allows GCC to be configured with the --with-cpu=power11 and
+--with-tune=power11 options.
+
+This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
+
+This patch adds support for using "power11" in the __builtin_cpu_is built-in
+function.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+	* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+	* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+	* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
+	* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR11 if -mcpu=power11.
+	* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define.
+	(POWERPC_MASKS): Add power11 isa bit.
+	(power11 cpu): Add power11 definition.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor.
+	* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11
+	support.
+	(rs6000_machine_from_flags): Likewise.
+	(rs6000_reassociation_width): Likewise.
+	(rs6000_adjust_cost): Likewise.
+	(rs6000_issue_rate): Likewise.
+	(rs6000_sched_reorder): Likewise.
+	(rs6000_sched_reorder2): Likewise.
+	(rs6000_register_move_cost): Likewise.
+	(rs6000_opt_masks): Likewise.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/rs6000.md (cpu attribute): Add power11.
+	* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag.
+	* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11.
+
 ==================== Branch work164-bugs, baseline ====================
 
+Add ChangeLog.bugs and update REVISION.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* ChangeLog.bugs: New file for branch.
+	* REVISION: Update.
+
 2024-04-08   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
-