[gcc r12-10319] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

[gcc r12-10319] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

[Kito Cheng]

https://gcc.gnu.org/g:d37be5c0413783c5459c5664b6ffb9f47acfca4e

commit r12-10319-gd37be5c0413783c5459c5664b6ffb9f47acfca4e
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Wed Feb 28 16:01:52 2024 +0800

    RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64
    
    atomic_compare_and_swapsi will use lr.w to do obtain the original value,
    which sign extends to DI.  RV64 only has DI comparisons, so we also need
    to sign extend the expected value to DI as otherwise the comparison will
    fail when the expected value has the 32nd bit set.
    
    gcc/ChangeLog:
    
            PR target/114130
            * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
            extend the expected value if needed.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/pr114130.c: New.
    
    Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
    (cherry picked from commit fd07a29e39f5347d6cef3e7042a32306f97a1719)

Diff:
---
 gcc/config/riscv/sync.md                  |  9 +++++++++
 gcc/testsuite/gcc.target/riscv/pr114130.c | 12 ++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 86b41e6b00a..9a9cb8be69a 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -129,6 +129,15 @@
    (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
   "TARGET_ATOMIC"
 {
+  if (word_mode != <MODE>mode && operands[3] != const0_rtx)
+    {
+      /* We don't have SI mode compare on RV64, so we need to make sure expected
+	 value is sign-extended.  */
+      rtx tmp0 = gen_reg_rtx (word_mode);
+      emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, <MODE>mode, 0));
+      operands[3] = simplify_gen_subreg (<MODE>mode, tmp0, word_mode, 0);
+    }
+
   emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
 						operands[3], operands[4],
 						operands[6], operands[7]));
diff --git a/gcc/testsuite/gcc.target/riscv/pr114130.c b/gcc/testsuite/gcc.target/riscv/pr114130.c
new file mode 100644
index 00000000000..cd0a4e8236c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114130.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
+#include <stdint-gcc.h>
+
+void foo(uint32_t *p) {
+    uintptr_t x = *(uintptr_t *)p;
+    uint32_t e = !p ? 0 : (uintptr_t)p >> 1;
+    uint32_t d = (uintptr_t)x;
+    __atomic_compare_exchange(p, &e, &d, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-times "sext.w\t" 1 } } */