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* [gcc(refs/users/meissner/heads/work164-bugs)] Revert all changes
@ 2024-04-12 16:26 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2024-04-12 16:26 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:94405026c6c064a9e08d9f956f0ce067b6002caa
commit 94405026c6c064a9e08d9f956f0ce067b6002caa
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 12 12:26:03 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/rs6000.md | 44 ++++----------------------------------------
1 file changed, 4 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 32b0fd056fa..f1f120199f3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6041,10 +6041,6 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6058,13 +6054,7 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6120,10 +6110,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6134,13 +6120,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], true);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6165,13 +6145,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], true);
- emit_insn (gen_floatdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6931,10 +6905,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6945,13 +6915,7 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID && TARGET_LFIWAX)
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work164-bugs)] Revert all changes
@ 2024-04-12 7:25 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2024-04-12 7:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d97e784f9887aece6d857e5790ea931ea6e044ee
commit d97e784f9887aece6d857e5790ea931ea6e044ee
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 12 03:25:09 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/rs6000.md | 44 ++++----------------------------------------
1 file changed, 4 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 251b5c486b0..f1f120199f3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6041,10 +6041,6 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6058,13 +6054,7 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6120,10 +6110,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6134,13 +6120,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], true);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6165,13 +6145,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatunsdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6931,10 +6905,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6945,13 +6915,7 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID && TARGET_LFIWAX)
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work164-bugs)] Revert all changes
@ 2024-04-09 21:37 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2024-04-09 21:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ad98381bc5234aacf9caf674b0c334c626fbf78b
commit ad98381bc5234aacf9caf674b0c334c626fbf78b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 9 17:37:42 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/fusion.md | 15 ---------------
gcc/config/rs6000/genfusion.pl | 22 ----------------------
gcc/config/rs6000/predicates.md | 9 ---------
gcc/config/rs6000/rs6000.md | 5 +----
4 files changed, 1 insertion(+), 50 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 5feedf83cad..4ed9ae1d69f 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -3055,18 +3055,3 @@
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
-
-;; ori_oris and xori_xoris fusion patterns generated by gen_wide_immediate
-(define_insn "*fuse_<IORXOR_OP>i_<IORXOR_OP>is"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (iorxor:DI
- (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "u32bit_cint_2_insns_operand" "n")))]
- "(TARGET_P10_FUSION)"
-{
- HOST_WIDE_INT value = INTVAL (operands[2]);
- operands[3] = GEN_INT (value & 0xffff);
- operands[4] = GEN_INT ((value >> 16) & 0xffff);
- return "<IORXOR_OP>i %0,%1,%3\;<IORXOR_OP>is %0,%0,%4";
-}
- [(set_attr "length" "8")])
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index b6f1016b830..2271be14bfa 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -367,28 +367,6 @@ EOF
}
}
-sub gen_wide_immediate
-{
- print <<"EOF";
-
-;; ori_oris and xori_xoris fusion patterns generated by gen_wide_immediate
-(define_insn "*fuse_<IORXOR_OP>i_<IORXOR_OP>is"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (iorxor:DI
- (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "u32bit_cint_2_insns_operand" "n")))]
- "(TARGET_P10_FUSION)"
-{
- HOST_WIDE_INT value = INTVAL (operands[2]);
- operands[3] = GEN_INT (value & 0xffff);
- operands[4] = GEN_INT ((value >> 16) & 0xffff);
- return "<IORXOR_OP>i %0,%1,%3\\;<IORXOR_OP>is %0,%0,%4";
-}
- [(set_attr "length" "8")])
-EOF
-}
-
gen_ld_cmpi_p10();
gen_logical_addsubf();
gen_addadd;
-gen_wide_immediate();
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 83f368b2916..d23ce9a77a3 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -282,15 +282,6 @@
(and (match_code "const_int")
(match_test "(0x80000000 + UINTVAL (op)) >> 32 == 0")))
-;; Return 1 if op is a 32-bit unsigned constant where the upper 16-bits is
-;; non-zero along with the lower 16-bits that needs two instructions (ORI/ORIS
-;; or XORI/XORIS to do the operation).
-(define_predicate "u32bit_cint_2_insns_operand"
- (and (match_code "const_int")
- (match_test "(INTVAL (op) >> 32) == 0")
- (match_test "(INTVAL (op) & 0xffff) != 0")
- (match_test "(INTVAL (op) & 0xffff0000) != 0")))
-
;; Return 1 if op is a constant 32-bit unsigned
(define_predicate "c32bit_cint_operand"
(and (match_code "const_int")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f626b68ebb2..1acd34ca0ee 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -822,9 +822,6 @@
(SF "TARGET_P8_VECTOR")
(DI "TARGET_POWERPC64")])
-;; Convert iorxor iterator into or/xor instruction
-(define_code_attr IORXOR_OP [(ior "or") (xor "xor")])
-
(include "darwin.md")
\f
;; Start with fixed-point load and store insns. Here we put only the more
@@ -3936,7 +3933,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand")
(iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand")
(match_operand:GPR 2 "non_logical_cint_operand")))]
- "<MODE>mode != DImode || !TARGET_P10_FUSION"
+ ""
[(set (match_dup 3)
(iorxor:GPR (match_dup 1)
(match_dup 4)))
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-04-12 16:26 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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