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* [gcc(refs/users/meissner/heads/work164-test)] Update TAR support.
@ 2024-04-15 20:44 Michael Meissner
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From: Michael Meissner @ 2024-04-15 20:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3212394be5a6ade7b60a0d126e7dcadee8a04fb2
commit 3212394be5a6ade7b60a0d126e7dcadee8a04fb2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 15 16:44:40 2024 -0400
Update TAR support.
2024-04-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_debug_reg_global): Correctly print TAR
register.
(rs6000_init_hard_regno_mode_ok): Correctly initial TAR register.
* config/rs6000/rs6000.md (mov<mode>_internal): Add support for TAR
register.
(movcc_<mode>): Likewise.
(movsf_hardfloat): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat6): Likewise.
(indirect_jump): Likewise.
(@indirect_jump<mode>_nospec): Likewise.
(<bd>tf_<mode>): Remove TAR register.
* lra-constraints.cc (lra_constraints): Add debug_rtx before raising an
error.
Diff:
---
gcc/config/rs6000/rs6000.cc | 5 +++--
gcc/config/rs6000/rs6000.md | 24 ++++++++++++------------
gcc/lra-constraints.cc | 9 ++++++---
3 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 72e26dc2afd..908ad5dcb58 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2304,7 +2304,7 @@ rs6000_debug_reg_global (void)
"vs");
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
- rs6000_debug_reg_print (TAR_REGNO, CTR_REGNO, "tar");
+ rs6000_debug_reg_print (TAR_REGNO, TAR_REGNO, "tar");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
@@ -2781,7 +2781,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
- rs6000_regno_regclass[TAR_REGNO] = LINK_OR_CTR_REGS;
+ rs6000_regno_regclass[TAR_REGNO] = TAR_REGS;
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
@@ -2801,6 +2801,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
+ reg_class_to_reg_type[(int)TAR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d422e1c184b..efd441f4911 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8069,7 +8069,7 @@
[(set (match_operand:QHI 0 "nonimmediate_operand"
"=r, r, wa, m, ?Z, r,
wa, wa, wa, v, ?v, r,
- wa, r, *c*l, *h")
+ wa, r, *wt*c*l, *h")
(match_operand:QHI 1 "input_operand"
"r, m, ?Z, r, wa, i,
wa, O, wM, wB, wS, wa,
@@ -8120,9 +8120,9 @@
(define_insn "*movcc_<mode>"
[(set (match_operand:CC_any 0 "nonimmediate_operand"
- "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
+ "=y,x,?y,y,r,r,r,r, r,*wt*c*l,r,m")
(match_operand:CC_any 1 "general_operand"
- " y,r, r,O,x,y,r,I,*h, r,m,r"))]
+ " y,r, r,O,x,y,r,I,*h, r,m,r"))]
"register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode)"
"@
@@ -8210,7 +8210,7 @@
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *wt*c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
@@ -8256,7 +8256,7 @@
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
"=!r, d, m, ?Z, ?d, ?r,
- f, !r, *c*l, !r, *h")
+ f, !r, *wt*c*l, !r, *h")
(match_operand:SD 1 "input_operand"
"m, ?Z, r, wx, r, d,
f, r, r, *h, 0"))]
@@ -8286,7 +8286,7 @@
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, *c*l, r, r, m, r,
+ "=r, *wt*c*l, r, r, m, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
@@ -8600,7 +8600,7 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- YZ, r, !r, *c*l, !r,
+ YZ, r, !r, *wt*c*l, !r,
*h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
@@ -8652,7 +8652,7 @@
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=Y, r, r, *c*l, r, r,
+ "=Y, r, r, *wt*c*l,r, r,
r, r, *h")
(match_operand:FMOVE64 1 "input_operand"
@@ -13501,14 +13501,14 @@
(define_insn "*indirect_jump<mode>"
[(set (pc)
- (match_operand:P 0 "register_operand" "wt,c,*l"))]
+ (match_operand:P 0 "register_operand" "c,*l"))]
"rs6000_speculate_indirect_jumps"
"b%T0"
[(set_attr "type" "jmpreg")])
(define_insn "@indirect_jump<mode>_nospec"
- [(set (pc) (match_operand:P 0 "register_operand" "wt,c,*l"))
- (clobber (match_operand:CC 1 "cc_reg_operand" "=y,y,y"))]
+ [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))
+ (clobber (match_operand:CC 1 "cc_reg_operand" "=y,y"))]
"!rs6000_speculate_indirect_jumps"
"crset %E1\;beq%T0- %1\;b $"
[(set_attr "type" "jmpreg")
@@ -13774,7 +13774,7 @@
(const_int 0)]))
(label_ref (match_operand 0))
(pc)))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:P 5 "=X,X,&r,r"))
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 10e3d4e4097..4e72aa2d078 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -5346,9 +5346,12 @@ lra_constraints (bool first_p)
continue;
}
if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
- internal_error
- ("maximum number of generated reload insns per insn achieved (%d)",
- MAX_RELOAD_INSNS_NUMBER);
+ {
+ debug_rtx (curr_insn);
+ internal_error
+ ("maximum number of generated reload insns per insn achieved (%d)",
+ MAX_RELOAD_INSNS_NUMBER);
+ }
new_insns_num++;
if (DEBUG_INSN_P (curr_insn))
{
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