ELF instruction for section and branch.

ELF instruction for section and branch.

[Gagneet Singh]

Hi!

I wish to enquire what is the equivalent for a assembly language section
in the GCC ELF format?

Also, we have a problem of getting the output in ELF format where a
branch instruction is accessing a label in the second section. 

Is this possible? 

Or is the Branch and Jump instruction PC relative in MIPS ELF format
also, so that they cannot be accessed over the sections. If this is so,
I have to come back to my original question - how are sections defined
in the output of GCC for MIPS ELF architecture files.

I am running the tool in Win32, with the GDB port of Tx39 architecture.
Hope this information is enough, if not please ask for any other
required information.

Thank You

Gagneet

Re: ELF instruction for section and branch.

[Richard Sandiford]

"Gagneet Singh" <gagneet@acmet.com> writes:
> I wish to enquire what is the equivalent for a assembly language section
> in the GCC ELF format?

I'm not quite sure what you mean here, but...

> Also, we have a problem of getting the output in ELF format where a
> branch instruction is accessing a label in the second section. 
>
> Is this possible? 

It sounds like you're asking about code such as:

        .section .text1
foo:    b        bar

        .section .text2
bar:

Is that right?  If so, then no, this isn't supported.  The assembler
can't calculate the branch offset because the distance between foo and
bar isn't known until link time.  And unfortunately, due to an infamous
problem with the MIPS ELF spec, there's no relocation that the assembler
can use either.

(The R_MIPS_PC16 relocation was probably designed for branches, but the
ELF spec says it gives a byte offset, whereas branch instructions need
a word offset.)

Richard

RE: ELF instruction for section and branch.

[Gagneet Singh]

Hi!

Thanx for the answer. 

In your example,
"
>         .section .text1
> foo:    b        bar
> 
>         .section .text2
> bar:
"

If we take "b  bar" as a 32-bit instruction, then to get the relocation
information, of the label "bar", we can calculate the 'bar' value using
a 16-bit offset. 

If so, then it would be a 16-bit relocation.

Am I correct in assuming this?



> -----Original Message-----
> From: Richard Sandiford [mailto:rsandifo@redhat.com] 
> Sent: Friday, 19 December, 2003 20:34 PM
> To: gagneet@acmet.com
> Cc: gcc-help@gcc.gnu.org; gcc@gcc.gnu.org
> Subject: Re: ELF instruction for section and branch.
> 
> 
> "Gagneet Singh" <gagneet@acmet.com> writes:
> > I wish to enquire what is the equivalent for a assembly language 
> > section in the GCC ELF format?
> 
> I'm not quite sure what you mean here, but...
> 
> > Also, we have a problem of getting the output in ELF format where a 
> > branch instruction is accessing a label in the second section.
> >
> > Is this possible?
> 
> It sounds like you're asking about code such as:
> 
>         .section .text1
> foo:    b        bar
> 
>         .section .text2
> bar:
> 
> Is that right?  If so, then no, this isn't supported.  The 
> assembler can't calculate the branch offset because the 
> distance between foo and bar isn't known until link time.  
> And unfortunately, due to an infamous problem with the MIPS 
> ELF spec, there's no relocation that the assembler can use either.
> 
> (The R_MIPS_PC16 relocation was probably designed for 
> branches, but the ELF spec says it gives a byte offset, 
> whereas branch instructions need a word offset.)
> 
> Richard
> 

Re: ELF instruction for section and branch.

[Richard Sandiford]

"Gagneet Singh" <gagneet@acmet.com> writes:
> In your example,
> "
>>         .section .text1
>> foo:    b        bar
>> 
>>         .section .text2
>> bar:
> "
>
> If we take "b  bar" as a 32-bit instruction, then to get the relocation
> information, of the label "bar", we can calculate the 'bar' value using
> a 16-bit offset. 
>
> If so, then it would be a 16-bit relocation.

Yes, but the point of what I said here:

>> It sounds like you're asking about code such as:
>> 
>>         .section .text1
>> foo:    b        bar
>> 
>>         .section .text2
>> bar:
>> 
>> Is that right?  If so, then no, this isn't supported.  The 
>> assembler can't calculate the branch offset because the 
>> distance between foo and bar isn't known until link time.  
>> And unfortunately, due to an infamous problem with the MIPS 
>> ELF spec, there's no relocation that the assembler can use either.
>> 
>> (The R_MIPS_PC16 relocation was probably designed for 
>> branches, but the ELF spec says it gives a byte offset, 
>> whereas branch instructions need a word offset.)

is that the official ELF spec does not define a suitable relocation.

Richard

RE: ELF instruction for section and branch.

[Gagneet Singh]

Hi!

Thanx for the answer.

So it would appear that we will not be able to generate ELF branch
across sections in MIPS architecture. But, is it possible for ELF
architecture as such, or 

"official ELF spec does not define a suitable relocation"

the above statement holds true for any architecture with ELF output. If
I wish to compile and link the example in the x86 architecture with ELF
format as output, how will I do that and specially is that possible??

Also, does GCC define sections in the assembly file as '.section .text1'
or is this example specific to an architecture??

Gagneet



> "Gagneet Singh" <gagneet@acmet.com> writes:
> > In your example,
> > "
> >>         .section .text1
> >> foo:    b        bar
> >> 
> >>         .section .text2
> >> bar:
> > "
> >
> > If we take "b  bar" as a 32-bit instruction, then to get the 
> > relocation information, of the label "bar", we can 
> calculate the 'bar' 
> > value using a 16-bit offset.
> >
> > If so, then it would be a 16-bit relocation.
> 
> Yes, but the point of what I said here:
> 
> >> It sounds like you're asking about code such as:
> >> 
> >>         .section .text1
> >> foo:    b        bar
> >> 
> >>         .section .text2
> >> bar:
> >> 
> >> Is that right?  If so, then no, this isn't supported.  The
> >> assembler can't calculate the branch offset because the 
> >> distance between foo and bar isn't known until link time.  
> >> And unfortunately, due to an infamous problem with the MIPS 
> >> ELF spec, there's no relocation that the assembler can use either.
> >> 
> >> (The R_MIPS_PC16 relocation was probably designed for
> >> branches, but the ELF spec says it gives a byte offset, 
> >> whereas branch instructions need a word offset.)
> 
> is that the official ELF spec does not define a suitable relocation.
> 
> Richard
> 

Re: ELF instruction for section and branch.

[Ian Lance Taylor]

"Gagneet Singh" <gagneet@acmet.com> writes:

> So it would appear that we will not be able to generate ELF branch
> across sections in MIPS architecture. But, is it possible for ELF
> architecture as such, or 
> 
> "official ELF spec does not define a suitable relocation"
> 
> the above statement holds true for any architecture with ELF output. If
> I wish to compile and link the example in the x86 architecture with ELF
> format as output, how will I do that and specially is that possible??

Any statement about whether a suitable relocation is available in ELF
is specific to a particular architecture.

You should be able to do cross-section jumps using i386 ELF.  The i386
branch instructions are simple 32-bit relocations, which are available
in i386 ELF.

> Also, does GCC define sections in the assembly file as '.section .text1'
> or is this example specific to an architecture??

It's specific to a particular target, though that particular form is
quite common.  When using gas, see:
    http://sources.redhat.com/binutils/docs-2.12/as.info/Section.html#Section

Ian

Re: ELF instruction for section and branch.

[Jamie Lokier]

Gagneet Singh wrote:
> I wish to compile and link the example in the x86 architecture with ELF
> format as output, how will I do that and specially is that possible??

It works fine with x86 and plenty of other architectures.

You may also find the ".subsection" directive useful, if all you need
is for some instructions to be out of line.  It will put the code in a
separate subsection at the end of the same section in the object file,
so the offset can be calculated at assembly time instead of link time.

-- Jamie

RE: ELF instruction for section and branch.

[Gagneet Singh]

I tried using it for MIPS but I think it is not defined there, but it
work perfectly for x86 ELF.
Will have to get more info on this from the MIPS people.

Thanx for the advice. 


> -----Original Message-----
> From: Jamie Lokier [mailto:jamie@shareable.org] 
> Sent: Sunday, 21 December, 2003 20:22 PM
> To: Gagneet Singh
> Cc: 'Richard Sandiford'; gcc@gcc.gnu.org; gcc-help@gcc.gnu.org
> Subject: Re: ELF instruction for section and branch.
> 
> 
> Gagneet Singh wrote:
> > I wish to compile and link the example in the x86 architecture with 
> > ELF format as output, how will I do that and specially is that 
> > possible??
> 
> It works fine with x86 and plenty of other architectures.
> 
> You may also find the ".subsection" directive useful, if all 
> you need is for some instructions to be out of line.  It will 
> put the code in a separate subsection at the end of the same 
> section in the object file, so the offset can be calculated 
> at assembly time instead of link time.
> 
> -- Jamie
> 

RE: ELF instruction for section and branch.

[Gagneet Singh]

Thank for the info, will just look it up.

I tried with the MIPS ELF output but was unable to get the desired
result. Even after compiling with GCC using the GCC port to the desired
architecture. 

The architecture I am using defines a section by the name '.text', but
if I try to make another section named '.text1' or anything similar it
issues an error saying "secbr.s:93: Error: Unknown pseudo-op:
`.text1'".

What can be the reason for this, does it mean that only one section can
be specified or is it that the section definition should have '.text'
preceding it. And the section is defined as a name of the function??

Gagneet

> -----Original Message-----
> From: Ian Lance Taylor [mailto:ian@wasabisystems.com] 
> Sent: Saturday, 20 December, 2003 21:09 PM
> To: gagneet@acmet.com
> Cc: gcc@gcc.gnu.org; gcc-help@gcc.gnu.org
> Subject: Re: ELF instruction for section and branch.
> 
> 
> "Gagneet Singh" <gagneet@acmet.com> writes:
> 
> > So it would appear that we will not be able to generate ELF branch 
> > across sections in MIPS architecture. But, is it possible for ELF 
> > architecture as such, or
> > 
> > "official ELF spec does not define a suitable relocation"
> > 
> > the above statement holds true for any architecture with 
> ELF output. 
> > If I wish to compile and link the example in the x86 
> architecture with 
> > ELF format as output, how will I do that and specially is that 
> > possible??
> 
> Any statement about whether a suitable relocation is 
> available in ELF is specific to a particular architecture.
> 
> You should be able to do cross-section jumps using i386 ELF.  
> The i386 branch instructions are simple 32-bit relocations, 
> which are available in i386 ELF.
> 
> > Also, does GCC define sections in the assembly file as '.section 
> > .text1' or is this example specific to an architecture??
> 
> It's specific to a particular target, though that particular 
> form is quite common.  When using gas, see:
>     
> http://sources.redhat.com/binutils/docs-2.12/as.info/Section.h
tml#Section

Ian

RE: ELF instruction for section and branch.

[Gagneet Singh]

I tried using it for MIPS but I think it is not defined there, but it
work perfectly for x86 ELF.
Will have to get more info on this from the MIPS people.

Thanx for the advice. 


> -----Original Message-----
> From: Jamie Lokier [mailto:jamie@shareable.org] 
> Sent: Sunday, 21 December, 2003 20:22 PM
> To: Gagneet Singh
> Cc: 'Richard Sandiford'; gcc@gcc.gnu.org; gcc-help@gcc.gnu.org
> Subject: Re: ELF instruction for section and branch.
> 
> 
> Gagneet Singh wrote:
> > I wish to compile and link the example in the x86 architecture with 
> > ELF format as output, how will I do that and specially is that 
> > possible??
> 
> It works fine with x86 and plenty of other architectures.
> 
> You may also find the ".subsection" directive useful, if all 
> you need is for some instructions to be out of line.  It will 
> put the code in a separate subsection at the end of the same 
> section in the object file, so the offset can be calculated 
> at assembly time instead of link time.
> 
> -- Jamie
> 

Re: ELF instruction for section and branch.

[Ian Lance Taylor]

"Gagneet Singh" <gagneet@acmet.com> writes:

> I tried with the MIPS ELF output but was unable to get the desired
> result. Even after compiling with GCC using the GCC port to the desired
> architecture. 
> 
> The architecture I am using defines a section by the name '.text', but
> if I try to make another section named '.text1' or anything similar it
> issues an error saying "secbr.s:93: Error: Unknown pseudo-op:
> `.text1'".
> 
> What can be the reason for this, does it mean that only one section can
> be specified or is it that the section definition should have '.text'
> preceding it. And the section is defined as a name of the function??

If you want help, you must provide a complete test case.  We can not
guess what you are doing.

If this is assembler source code, the question should go to a binutils
list, not a gcc list.  See http://sourceware.org/binutils/.

Ian

RE: ELF instruction for section and branch.

[Gagneet Singh]

Hi!

> If you want help, you must provide a complete test case.  We 
> can not guess what you are doing.

Sorry about leaving out the test case examples...

Also, I did not know about the binutils mailing list and thought that
this list will be the one for the Assembler porting also.. my apologies
again..

Well! For now I am sending the example (sending the complete source for
both MIPS and Intel) to this list until my confirmation about the other
oe comes in...  This is just as a followup and closeure of this thread.

MIPS Assembly Output:
----------------------
;==========================================================
;Created on  :  18th December 2003

;Created by  :  Gagneet Singh

;Description : 
; This test file is to test the behaviour of the branch instruction with
; a label. The label is defined in a seperate code section. 
; I have as yet to succeed in creating a assembly output from a C file, 
; which simulates the condition given above. 
; Thus, the assembly file is being hand-coded.

;Test case History:
; Created for testing the result of 
; "a branch instruction is referencing a label defined in another
section".

;Phenomenon:
; For IEEE the file is being processed properly. This has been
; seen using the MIPS debugger. But, for ELF formats
; when tested using the GDB simulator created for ELF output, it
; is not.

;Hypothesis: 
; In the debugger if we view the 'Symbols' window we see that the 
; assembly file has been described with two sections - data and code.
; The data section is of size 4 bytes, while the code section comprises
; both the code sections and is of size 80 bytes.

;Expected behaviour:
; The label given at TestNode2 is referenced properly in IEEE format
when 
; the branch instruction at TestNode1 references it. The code flow goes
to
; the address referenced by the label L1 (TestNode1).
; The ELF behaviour is not known.

;Reference: Mails from the GCC Mailing List 
;===============================================================
	module section_branch_asm_c
n_data section data medium align=4,4
	align 4
	public _globalVar
_globalVar:
	align 4
	dw 10
f_code section code isa32 align=4,4
	align 4
	public _main
_main:
	addiu	sp, sp, -8
	sw	ra, 4(sp)
	sw	r16, 0(sp)
	ori	r13, r0, 0xa
	ori	r2, r0, 0x1
	beq	r2, r0, L1
	nop	
	addu	r16, r13, r0
	addu	r4, r13, r0
	jal	_fsiBranchLabel
	nop	

;TestNode2
L1:
	addu	r2, r16, r0
	j	L0
	nop	
L0:
	lw	ra, 4(sp)
	lw	r16, 0(sp)
	addiu	sp, sp, 8
	jr	ra
	nop

f_code section code isa32 align=4,4
	align 4
	public _fsiBranchLabel
_fsiBranchLabel:
	symbol_a "",9,0,4
	addu	r12, r4, r0
	slti	r2, r4, 10

;TestNode1
	bne	r2, r0, L1
	nop	
	addiu	r12, r4, 1
	sw	r4, sdaoff(_globalVar)(gp)
L4:
	addu	r2, r12, r0
	j	L3
	nop	
L3:
	jr	ra
	nop

	end

====================================================

GCC Intel i686 Assembly Language Output:
-------------------------------
#==========================================================
#Created on  :  18th December 2003

#Created by  :  Gagneet Singh

#Description : 
# This test file is to test the behaviour of the branch instruction with
# a label. The label is defined in a separate code section. 
# I have as yet to succeed in creating a assembly output from a C file, 
# which simulates the condition given above. 
# Thus, the assembly file is being hand-coded.

#Test case History:
# Created for testing the result of 
# "a branch instruction is referencing a label defined in another
section".

#Phenomenon:
# Only one section can be defined by the '.text', if I substitute
# the section name  as '.text1' if gives and error.

#Hypothesis: 
# Issues an error for TestNode3 saying "secbr.s:93: Error: Unknown
pseudo-op: 
# `.text1'".

#Expected behaviour:
# As yet to determine, otherwise the file should compile and link
properly.

#Reference:
#============================================================
	.file	1 "secbr.c"

 # -G value = 8, Cpu = 3000, ISA = 1
 # GNU C version 2.7 (mips-tx39-elf) compiled by GNU C version
2.7-97r1a.
 # options passed: 
 # options enabled:  -fpeephole -ffunction-cse -fkeep-static-consts
 # -freg-struct-return -fcommon -fverbose-asm -fgnu-linker -mgas
 # -msoft-float -meb -m3900 -mcpu=3000

gcc2_compiled.:
__gnu_compiled_c:
	.globl	globalVar
	.sdata
	.align	2
globalVar:
	.word	10

	.text
	.align	2
	.globl	main
	.ent	main
main:
	.frame	$fp,16,$31		# vars= 8, regs= 2/0, args= 0,
extra= 0
	.mask	0xc0000000,-4
	.fmask	0x00000000,0
	subu	$sp,$sp,16
	sw	$31,12($sp)
	sw	$fp,8($sp)
	move	$fp,$sp
	jal	__main
	li	$2,10			# 0x0000000a
	sw	$2,0($fp)
	lw	$2,0($fp)
	li	$3,10			# 0x0000000a
	bne	$2,$3,$L2
	lw	$2,0($fp)
	sw	$2,4($fp)
	addu	$2,$2,1
	sw	$2,0($fp)
	lw	$4,4($fp)
	jal	fsiBranchLabel
	sw	$2,0($fp)

#TestNode2
$L2:
	lw	$3,4($fp)
	move	$2,$3
	b	$L1
$L1:
	move	$sp,$fp			# sp not trusted here
	lw	$31,12($sp)
	lw	$fp,8($sp)
	addu	$sp,$sp,16
	j	$31
	.end	main

#TestNode3
	.text
	.align	2
	.globl	fsiBranchLabel
	.ent	fsiBranchLabel
fsiBranchLabel:
	.frame	$fp,16,$31		# vars= 8, regs= 1/0, args= 0,
extra= 0
	.mask	0x40000000,-8
	.fmask	0x00000000,0
	subu	$sp,$sp,16
	sw	$fp,8($sp)
	move	$fp,$sp
	sw	$4,0($fp)
	lw	$2,0($fp)
	slt	$3,$2,10
#TestNode1	
	bne	$3,$0,$L1
	lw	$2,0($fp)
	sw	$2,globalVar
	addu	$2,$2,1
	sw	$2,0($fp)
$L4:
	lw	$3,0($fp)
	move	$2,$3
	b	$L2
$L3:
	move	$sp,$fp			# sp not trusted here
	lw	$fp,8($sp)
	addu	$sp,$sp,16
	j	$31
	.end	fsiBranchLabel

Re: ELF instruction for section and branch.

[Ian Lance Taylor]

"Gagneet Singh" <gagneet@acmet.com> writes:

> #Hypothesis: 
> # Issues an error for TestNode3 saying "secbr.s:93: Error: Unknown
> pseudo-op: 
> # `.text1'".

This is indeed an unknown pseudo-op.

You want the .section pseudo-op.  .text is a special case.  See the
assembler manual.

Ian

RE: ELF instruction for section and branch.

[Gagneet Singh]

MAIL:
-----

We have been analyzing the information you had sent, regarding:

> It sounds like you're asking about code such as:
> 
>         .section .text1
> foo:    b        bar
> 
>         .section .text2
> bar:
>
> Is that right?  If so, then no, this isn't supported.  The
> assembler can't calculate the branch offset because the 
> distance between foo and bar isn't known until link time.  
> And unfortunately, due to an infamous problem with the MIPS 
> ELF spec, there's no relocation that the assembler can use either.
> 
> (The R_MIPS_PC16 relocation was probably designed for
> branches, but the ELF spec says it gives a byte offset, 
> whereas branch instructions need a word offset.)


We have come to a conclusion that if we branch to a label local to the
section in which the branch is invoked and then jump to the desired
location in the other section it should solve the problem. 

	.section .text1
foo:	
	b	L1

L1:
	j	bar


	.section .text2
bar:
	add	r4, r5, r6


Are we correct in assuming this?






> -----Original Message-----
> From: Richard Sandiford [mailto:rsandifo@redhat.com] 
> Sent: Friday, 19 December, 2003 20:34 PM
> To: gagneet@acmet.com
> Cc: gcc-help@gcc.gnu.org; gcc@gcc.gnu.org
> Subject: Re: ELF instruction for section and branch.
> 
> 
> "Gagneet Singh" <gagneet@acmet.com> writes:
> > I wish to enquire what is the equivalent for a assembly language 
> > section in the GCC ELF format?
> 
> I'm not quite sure what you mean here, but...
> 
> > Also, we have a problem of getting the output in ELF format where a 
> > branch instruction is accessing a label in the second section.
> >
> > Is this possible?
> 
> It sounds like you're asking about code such as:
> 
>         .section .text1
> foo:    b        bar
> 
>         .section .text2
> bar:
> 
> Is that right?  If so, then no, this isn't supported.  The 
> assembler can't calculate the branch offset because the 
> distance between foo and bar isn't known until link time.  
> And unfortunately, due to an infamous problem with the MIPS 
> ELF spec, there's no relocation that the assembler can use either.
> 
> (The R_MIPS_PC16 relocation was probably designed for 
> branches, but the ELF spec says it gives a byte offset, 
> whereas branch instructions need a word offset.)
> 
> Richard
> 

Re: ELF instruction for section and branch.

[Richard Sandiford]

[This is very off-topic for the gcc lists.  I've kept it cc'ed so that
 people know about the reply, but please respond privately.]

"Gagneet Singh" <gagneet@acmet.com> writes:
> We have come to a conclusion that if we branch to a label local to the
> section in which the branch is invoked and then jump to the desired
> location in the other section it should solve the problem. 
>
> 	.section .text1
> foo:	
> 	b	L1
>
> L1:
> 	j	bar
>
>
> 	.section .text2
> bar:
> 	add	r4, r5, r6
>
>
> Are we correct in assuming this?

Well, this example doesn't make much sense: you could simply have
"foo: j bar".  But yes, you can implement conditional branches to
bar using this sort of scheme.

Richard

ELF instruction for section and branch.

[Gagneet Singh]

Hi!

I wish to enquire what is the equivalent for a assembly language section
in the GCC ELF format?

Also, we have a problem of getting the output in ELF format where a
branch instruction is accessing a label in the second section. 

Is this possible? 

Or is the Branch and Jump instruction PC relative in MIPS ELF format
also, so that they cannot be accessed over the sections. If this is so,
I have to come back to my original question - how are sections defined
in the output of GCC for MIPS ELF architecture files.

I am running the tool in Win32, with the GDB port of Tx39 architecture.
Hope this information is enough, if not please ask for any other
required information.

Thank You

Gagneet