Re: Atomic accesses on ARM microcontrollers

[David Brown <david.brown@hesbynett.no>]

On 10/10/2020 21:43, David Brown wrote:
> 

> If I understand you correctly, you mean that I can simply implement my
> own version of __atomic_load_8 and other functions in libatomic?
> 
> I had a quick test (using the godbolt.org online compiler).
> 
> By adding this to my file:
> 
> extern inline
> uint64_t __atomic_load_8(const volatile void * p, int order) {
>     (void) order;
>     const volatile uint64_t * q = (const volatile uint64_t *) p;
>     return *q;
> }
> 
> then a straight load of a 64-bit atomic becomes a single "ldrd" load
> double register instruction, which is optimal for this processor.  (In a
> finished solution, I'd want to check that this is correct for different
> flags - possibly adding function attributes for optimisation or inline
> assembly to ensure that it is always correct.  But that's a detail for
> me to check.)
> 
> The same worked for __atomic_store_8.
> 

Just to be clear here, in case anyone else is reading these posts and
uses them for their own code, a single "strd" store double register
operation is not, in general, strong enough for the __atomic_store_8 on
the Cortex-M devices.  If the processor gets an interrupt while
executing the strd, it may have stored the first half of the new value
but not the second half.  If the interrupting code then reads the
object, it will get an inconsistent read.  (If that can't occur - maybe
only your interrupt routine changes the object - there's no problem.)
So the __atomic_store_8 should disable interrupts around the write.

(And again to be clear, this is for single-core microcontrollers with
bare metal, rather than for multi-core or with a host host.)

> (The general load/store functions are a bit more involved, as are the
> read-modify-write atomic functions.)
>