Re: Atomic accesses on ARM microcontrollers

[David Brown <david.brown@hesbynett.no>]

On 11/10/2020 14:34, Toby Douglass wrote:
> On 11/10/2020 14:16, David Brown wrote:

> 
>>> I could be wrong, but I think the only way you can do this with atomics
>>> is copy-on-write.  Make a new copy of the data, and use an atomic to
>>> flip a pointer, so the readers move atomically from the old version to
>>> the new version.
>>
>> I've been thinking a bit more about this, inspired by your post here.
>> And I believe you are correct - neither ldrex/strex nor load/store
>> double register is sufficient for 64-bit atomic accesses on the 32-bit
>> ARM, even for plain reads and writes.
> 
> No - I think you can have 64-bit atomic stores on a 32-bit CPU.  There
> *is* a double word atomic compare-and-swap.

Certainly it is possible - if the cpu has such an instruction.  The
Cortex-M cores do not.

>  If you define a 64-bit
> integer type, and use it with __atomic_compare_exchange_n(), you should
> get a 64-bit atomic swap.  In older versions of the library, I actually
> had inline assembly for this, but I realised in the end I could in fact
> get GCC to emit the correct code.
> 
> However, I don't understand how a double-word atomic store helps you. 
> If you have an arbitrarily-sized block of memory to update atomically,
> how can you use a 64-bit atomic store to do this?
> 

It would not help for arbitrary blocks of memory, but it /would/ help
for 64-bit blocks.  And that would cover a sizeable majority of
use-cases for me.

>> One thing we can all be sure about - this stuff is difficult, it needs a
>> /lot/ of thought, and the documentation is often poor on the critical
>> details.
> 
> Amen.
>