Multi-line Packed-Bit Int SiMD Maths : Relevance HDR, WCG, ML Machine Learning (Most advantaged ADDER Maths)

Multi-line Packed-Bit Int SiMD Maths : Relevance HDR, WCG, ML Machine Learning (Most advantaged ADDER Maths)

[Duke Abbaddon]

Multi-line Packed-Bit Int SiMD Maths : Relevance HDR, WCG, ML Machine
Learning (Most advantaged ADDER Maths)

The rules of multiple Maths with lower Bit widths into SiMD 256Bit
(example) 64Bit & 128Bit & 512Bit can be used

In all methods you use packed bits per save, so single line save or
load, Parallel, No ram thrashing.

You cannot flow a 16Bit block into another segment (the next 16Bit block)

Addition is the only place where 16Bit * 4 = 64Bit works easily, but
when you ADD or - you can only roll to the lowest boundary of each
16Bit segment & not into the higher or lower segment.

A: In order to multiply you need adaptable rules to division & multiply
B: you need a dividable Maths unit with And OR & Not gates to segment
the registered Mul SiMD Unit..

In the case of + * you need to use single line rule addition (no over
flow per pixel)..
& Either Many AND-OR / Not gate layer or Parallel 16Bit blocks..

You can however painful as it is Multi Load & Zero remainder registers
& &or X or Not remainder 00000 on higher depth instructions & so
remain pure!

8Bit blocks are a bit small and we use HDR & WCG, So mostly pointless!

We can however 8Bit Write a patch of pallete & sub divide our colour
pallet & Light Shadow Curves in anything over 8Bit depth colour,

In the case of Intel 8Bit * 8 Inferencing unit : 16 Bit Colour in
probably (WCG 8 * 8) + (HDR 8 * 8) Segments,

In any case Addition is fortunately what we need! so with ADD we can
use SiMD & Integer Today.

Rupert S

https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html

https://science.n-helix.com/2022/10/ml.html

https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html

https://science.n-helix.com/2023/06/map.html