secondary_reload not called during IRA

secondary_reload not called during IRA

[Aurelien Buhrig]

Hi,

Sorry about spamming this mailing list, but I need an advice once again...
I've switched gcc branch from 4.3.6 to 4.6.1 for my backend, and I
have a new reload problem.

During the IRA pass, the following insn:

(insn 18 218 19 4 (set (subreg:SI (reg:DI 20 [ D.2998 ]) 4)
        (reg/v:SI 37 [ arg_a ])) ../.././gcc/dp-bit.c:1385 24 {movsi}
     (nil))


is transformed into :

(insn 18 253 254 4 (set (reg:SI 7 a0)
        (reg/v:SI 2 r2 [orig:37 arg_a ] [37]))
../.././gcc/dp-bit.c:1385 24 {movsi}
     (nil))

(insn 254 18 19 4 (set (mem/c:SI (plus:PSI (reg/f:PSI 12 a5)
                (const_int -16 [0xfffffffffffffff0])) [8 %sfp+-16 S4 A16])
        (reg:SI 7 a0)) ../.././gcc/dp-bit.c:1385 24 {movsi}
     (nil))


The problem is that my TARGET_SECONDARY_RELOAD is not called with last
mem rtx before reloading (and a0 class is not valid for memory moves)
and thus I cannot force the right reg class for such moves.
Do I miss something ?

Thanks,
Aurélien

Re: secondary_reload not called during IRA

[Aurelien Buhrig]

> Hi,
>
> Sorry about spamming this mailing list, but I need an advice once again...
> I've switched gcc branch from 4.3.6 to 4.6.1 for my backend, and I
> have a new reload problem.
>
> During the IRA pass, the following insn:
>
> (insn 18 218 19 4 (set (subreg:SI (reg:DI 20 [ D.2998 ]) 4)
>        (reg/v:SI 37 [ arg_a ])) ../.././gcc/dp-bit.c:1385 24 {movsi}
>     (nil))
>
>
> is transformed into :
>
> (insn 18 253 254 4 (set (reg:SI 7 a0)
>        (reg/v:SI 2 r2 [orig:37 arg_a ] [37]))
> ../.././gcc/dp-bit.c:1385 24 {movsi}
>     (nil))
>
> (insn 254 18 19 4 (set (mem/c:SI (plus:PSI (reg/f:PSI 12 a5)
>                (const_int -16 [0xfffffffffffffff0])) [8 %sfp+-16 S4 A16])
>        (reg:SI 7 a0)) ../.././gcc/dp-bit.c:1385 24 {movsi}
>     (nil))
>
>
> The problem is that my TARGET_SECONDARY_RELOAD is not called with last
> mem rtx before reloading (and a0 class is not valid for memory moves)
> and thus I cannot force the right reg class for such moves.
> Do I miss something ?


In fact, during reload replace pass, the (subreg:SI (reg:DI 20 [
D.2998 ]) 4) operand is reloaded into registers of class ADDRESS_REGS
(this is permitted), and then is spilled.
But my target do not permit spilling ADDRESS_REGS, in modes other than
PSImode... how to deal with this ?

I found a workaround by inverting alternatives in the movsi pattern so
that the first "best" alternative is the one with DATA_REGS class regs
which can be spilled. But it seems unsafe...

Thanks,
Aurélien