makefile error

makefile error

[Parikshat Dubey]

Hi All,

I am making a makefile as following:
/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*
/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*
CC = /usr/sfw/bin/g++

INCLUDE = -I/usr/local/include/directfb \  #
	  -I/usr/local/include/direct-internal \
	  -I/usr/include \
	  -I../include
LD = $(CC)

LDFLAGS =

CCFLAGS = -D_REENTRANT \
	 -D_GNU_SOURCE \
	 -O2 \
	-g -Wall\


LIBS = -lz \
       -lpthread \
       -ldirectfb \
       -lfusion \
       -ldirect \
       -ldl \
       -lfbclient \
       -lm \
       -g \
       -lpam \
       -llibs

OBJS = NM.o \
	File.o \
	Queue.o

NM.o:NM.c File.h Queue.h header.h
	$(CC) -c NM.c $(CFLAGS) $(INCLUDE) $(LIBS)
File.o:File.c File.h
	$(CC) -c File.c $(CFLAGS) $(INCLUDE) $(LIBS)
Queue.o:Queue.c Queue.h header.h
	$(CC) -c Queue.c $(CFLAGS) $(INCLUDE) $(LIBS)
#all:nodemanager
nodemanager:$(OBJS)
	$(LD) $(LDFLAGS) $(CFLAGS) $(OBJS) $(INCLUDE) $(LIBS)  -o nodemanager
clean:rm *.o nodemanager

/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*
/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*
i am getting the following errors:
/usr/sfw/bin/g++ -c NM.c  -I/usr/local/include/directfb 
-I/usr/local/include/direct-internal -I/usr/include -I../include 
-I/usr/sfw/lib/ -lz -lpthread -ldirectfb -lfusion -ldirect -ldl -lfbclient 
-lm -g -lpam -llibs
g++: -lz: linker input file unused because linking not done
g++: -lpthread: linker input file unused because linking not done
g++: -ldirectfb: linker input file unused because linking not done
g++: -lfusion: linker input file unused because linking not done
g++: -ldirect: linker input file unused because linking not done
g++: -ldl: linker input file unused because linking not done
g++: -lfbclient: linker input file unused because linking not done
g++: -lm: linker input file unused because linking not done
g++: -lpam: linker input file unused because linking not done
g++: -llibs: linker input file unused because linking not done

I went to gcc.gnu.org and got someinputs also e.g. giving --llibs option 
also but after that its giving :
usr/sfw/bin/g++ -c NM.c  -I/usr/local/include/directfb 
-I/usr/local/include/direct-internal -I/usr/include -I../include 
-I/usr/sfw/lib/ -lz -lpthread -ldirectfb -lfusion -ldirect -ldl -lfbclient 
-lm -g -lpam -llibs.

the above mentioned source files are simple sourcr files and having sockets 
and threads used. pLese help me out.I am in great trouble.I think i donot 
have the required libraries.

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Re: makefile error

[Daniel Llorens del Río]

On 11 May, 2006, at 21:00, Parikshat Dubey wrote:

> LIBS = -lz \
>       -lpthread \
>       -ldirectfb \
>       -lfusion \
>       -ldirect \
>       -ldl \
>       -lfbclient \
>       -lm \
>       -g \
>       -lpam \
>       -llibs
>
> OBJS = NM.o \
> 	File.o \
> 	Queue.o
>
> NM.o:NM.c File.h Queue.h header.h
> 	$(CC) -c NM.c $(CFLAGS) $(INCLUDE) $(LIBS)
> File.o:File.c File.h
> 	$(CC) -c File.c $(CFLAGS) $(INCLUDE) $(LIBS)
> Queue.o:Queue.c Queue.h header.h
> 	$(CC) -c Queue.c $(CFLAGS) $(INCLUDE) $(LIBS)
> #all:nodemanager
> nodemanager:$(OBJS)
> 	$(LD) $(LDFLAGS) $(CFLAGS) $(OBJS) $(INCLUDE) $(LIBS)  -o nodemanager
> clean:rm *.o nodemanager

> i am getting the following errors:
> /usr/sfw/bin/g++ -c NM.c  -I/usr/local/include/directfb -I/usr/ 
> local/include/direct-internal -I/usr/include -I../include -I/usr/ 
> sfw/lib/ -lz -lpthread -ldirectfb -lfusion -ldirect -ldl -lfbclient  
> -lm -g -lpam -llibs
> g++: -lz: linker input file unused because linking not done
> g++: -lpthread: linker input file unused because linking not done
> g++: -ldirectfb: linker input file unused because linking not done
> g++: -lfusion: linker input file unused because linking not done
> g++: -ldirect: linker input file unused because linking not done
> g++: -ldl: linker input file unused because linking not done
> g++: -lfbclient: linker input file unused because linking not done
> g++: -lm: linker input file unused because linking not done
> g++: -lpam: linker input file unused because linking not done
> g++: -llibs: linker input file unused because linking not done

Take the $(LIBS) out of these lines:

> NM.o:NM.c File.h Queue.h header.h
> 	$(CC) -c NM.c $(CFLAGS) $(INCLUDE) $(LIBS)
> File.o:File.c File.h
> 	$(CC) -c File.c $(CFLAGS) $(INCLUDE) $(LIBS)
> Queue.o:Queue.c Queue.h header.h
> 	$(CC) -c Queue.c $(CFLAGS) $(INCLUDE) $(LIBS)

Makefile Issue

[Parikshat Dubey]

Hi All!

I am stuck with one big problem as i have to spawn seven modules.

Module1,Module2,Module3,Module4,Module5,Module6,Module7.That is all these 
seven modules are running on one node or system.There is one more module you 
can name it 'Spawn Module' which will spawn all the seven modules i.e. spawn 
module will start all these modules. I am stuck .

I donot know what to do?Whether to write separate make file for each module  
from module 1 to module 7
and make a separate make file for spawn module which will  use all the makes 
of module 1 to module 7(I know how to write makefile but I donot know how to 
use all the separate makes for each module to make one final makefile if 
this is the case.)
Or
to write only one makefile and no need of making separate makefiles.

Can any body help me out.I need the solution as early as possible as things 
have halted for me right now.I will be really thankful and grateful if 
somebody will help me out.

ThanksandRegards
ParikshatDubey

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Re: Makefile Issue

[Perry Smith]

Well, of course, you could do any of those approaches.  None of them  
will be significantly different.

I would assume that to make Modules 1-7, the process is very  
similar.  If you go the separate makefile route, I would put the  
common things in a common make file and then include it in the  
module1-7 makefiles.  (It does not need to say "makefile" -- it could  
be named anything.)

The top level makefile can invoke make with the other makefiles using  
the -f option: make -f module1.mk for example.  (the .mk suffix is  
just something I made up -- its not significant to make.)  So you  
would have seven of those lines in the top level makefile.

I would try hard to have one makefile if that is plausible.  The  
reason is that for a change to a file that is not common to all the  
modules, only the minimum amount of work will be done to get things  
recompiled.  But, the separate calls to make will not cost time much  
either.

With GNU's make, you can have target specific variables.  So, for  
example, the list of object files needed for each module can be  
specified all in the same makefile using the same name for the  
macro.  Then the macro that does the link will pick the target  
specific value when it does the link for each particular target  
(module in this case).

For clarity, you could have these put into separate files and then  
include them into one master makefile.  Or, as I mentioned before,  
you could have the master makefile invoke make separately for each  
module.

Good luck,
Perry


On May 13, 2006, at 3:14 AM, Parikshat Dubey wrote:

> Hi All!
>
> I am stuck with one big problem as i have to spawn seven modules.
>
> Module1,Module2,Module3,Module4,Module5,Module6,Module7.That is all  
> these seven modules are running on one node or system.There is one  
> more module you can name it 'Spawn Module' which will spawn all the  
> seven modules i.e. spawn module will start all these modules. I am  
> stuck .
>
> I donot know what to do?Whether to write separate make file for  
> each module  from module 1 to module 7
> and make a separate make file for spawn module which will  use all  
> the makes of module 1 to module 7(I know how to write makefile but  
> I donot know how to use all the separate makes for each module to  
> make one final makefile if this is the case.)
> Or
> to write only one makefile and no need of making separate makefiles.
>
> Can any body help me out.I need the solution as early as possible  
> as things have halted for me right now.I will be really thankful  
> and grateful if somebody will help me out.
>
> ThanksandRegards
> ParikshatDubey
>
> _________________________________________________________________
> Get Marriage Proposals by Email. Join FREE! http://www.shaadi.com/ 
> matrimonial-banners/landingpage-jun06.php?ptnr=msnhottag
>
>

MakeFile Issue

[Parikshat Dubey]

Hi all!

i am writing  makefile for whole project.I am stuck with one problem.I hope 
i will get some assistance from you as i got it before also.The problem goes 
like this:

I have toplevel folder project which contains 20 
subdirectories(modules).Project Folder also contains Makefilke  which will 
use all the source files and headers in each of the subdirectory or module 
to produce object files and then integrating all these object files to 
produce final target or exe.each module contains source files and header 
files respective to that module.The problem which i was getting is to how i 
mention the source files and header files containing in subdirectory 1  or 
for that matter in subdirectory 2 and so on in toplevel directory.

Note1: I donot want to create a makefile for each module.Instead i want to 
make only one Makefile which will take all the source files and header files 
from the respective modules.

Note2: I want to know how i can mention in top level makefile the source 
files from subdirectory1 or subdirectory 2 so as it can take source files 
from the respective subdirectories and produce respective targets obviously 
objectfiles. and how i can mention the object files from the respective 
folders if it produces so.

Project Folder contains
a)20 subdirectories(modules)Each subdirectory is a module and contains 
source and header files pretaining to that module.The source file in all 
these modules doesnot contain main function.There is only one main function 
in main.c which is containing in top level folder project.
b)MakeFile
c)main.c which contains main() function


Thanks & Regards
Parikshat Dubey

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MakeFile Issue

[Parikshat Dubey]

Hi all!

i am writing  makefile for whole project.I am stuck with one problem.I hope 
i will get some assistance from you as i got it before also.The problem goes 
like this:

I have toplevel folder project which contains 20 
subdirectories(modules).Project Folder also contains Makefilke  which will 
use all the source files and headers in each of the subdirectory or module 
to produce object files and then integrating all these object files to 
produce final target or exe.each module contains source files and header 
files respective to that module.The problem which i was getting is to how i 
mention the source files and header files containing in subdirectory 1  or 
for that matter in subdirectory 2 and so on in toplevel directory.

Note1: I donot want to create a makefile for each module.Instead i want to 
make only one Makefile which will take all the source files and header files 
from the respective modules.

Note2: I want to know how i can mention in top level makefile the source 
files from subdirectory1 or subdirectory 2 so as it can take source files 
from the respective subdirectories and produce respective targets obviously 
objectfiles. and how i can mention the object files from the respective 
folders if it produces so.

Project Folder contains
a)20 subdirectories(modules)Each subdirectory is a module and contains 
source and header files pretaining to that module.The source file in all 
these modules doesnot contain main function.There is only one main function 
in main.c which is containing in top level folder project.
b)MakeFile
c)main.c which contains main() function


Thanks & Regards
Parikshat Dubey

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Makefile Issue

[Parikshat Dubey]

Hi all!

i am writing  makefile for whole project.I am stuck with one problem.I hope 
i will get some assistance from you as i got it before also.The problem goes 
like this:

I have toplevel folder project which contains 20 
subdirectories(modules).Project Folder also contains Makefilke  which will 
use all the source files and headers in each of the subdirectory or module 
to produce object files and then integrating all these object files to 
produce final target or exe.each module contains source files and header 
files respective to that module.The problem which i was getting is to how i 
mention the source files and header files containing in subdirectory 1  or 
for that matter in subdirectory 2 and so on in toplevel directory.

Note1: I donot want to create a makefile for each module.Instead i want to 
make only one Makefile which will take all the source files and header files 
from the respective modules.

Note2: I want to know how i can mention in top level makefile the source 
files from subdirectory1 or subdirectory 2 so as it can take source files 
from the respective subdirectories and produce respective targets obviously 
objectfiles. and how i can mention the object files from the respective 
folders if it produces so.

Project Folder contains
a)20 subdirectories(modules)Each subdirectory is a module and contains 
source and header files pretaining to that module.The source file in all 
these modules doesnot contain main function.There is only one main function 
in main.c which is containing in top level folder project.
b)MakeFile
c)main.c which contains main() function

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Re: Makefile issue

[Dima Sorkin]

On 7/3/06, Parikshat Dubey  wrote:
> c3.o:c3.c
>               $(CC)   -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<
>
> all:parikshit
> $(CC) -$(OBJS)  -$INCLUDE  -$(CFLAGS) -$LIBS --g -o parikshit
>
>
> As far as my knowledge goes '$< ' will automatically search the mentioned
> source file in the folder mentioned by SRC .for example in this case
> a1.o:a1.c
>               $(CC)  -$INCLUDE -$(CFLAGS)  -I.  -I$(SRC)  -c $<
> '$<' will automatically search the source file in the path mentioned by
> SRC(/Module/src) macro.
> i.e.above thing will automatically search source file a1.c in /Module/src/
> Module1/a1.c

No. "-I" is tells the _gcc_compiler_ where to look for "include"-files.
The Make program does not account for this, it cannot know.
There are ways to supply search paths for _make_ , but you will
have to read a lot of documentation, writing makefiles is a mastery
of itself. You may read

aegis.sourceforge.net/auug97.pdf
http://make.paulandlesley.org/autodep.html

Dima.

P.S.
 By the way, the lines of the form
"               $(CC)   -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<"
are redundant, make generates these calls by itself.

Makefile issue

[Parikshat Dubey]

Hi folks!

Friends I am preparing a make file but its giving target not needed by 
a1.c.target a1.o stop.
Here is the procedure
CC=/usr/sfw/bin/gcc
CFLAGS=-g -Wall
SRC=/Module/src
INCLUDE=/usr/include \
              /Module/header
              //path for header files gtk,gdk,atk,pango etc.
LIBS       =lsocket \
                lnsl \
                lpthread \
               path for library packages for gtk,gdk etc.

#MODULE 1 has following files a1.c ,a2.c,a3.c and a1.h,a2.h and a3.h
#MODULE 2 has following files b1.c ,b2.c,b3.c and b1.h,b2.h,b3.h
#MODULE 3 has following files c1.c ,c2.c,c3.c and c1.h,c2.h,c3.h

#There is a top level folder called Module which contains src and header 
subfolders.
#In src subfolder contain module1,2 and 3 which contains source 
filesrespective to the module and #in /module/header contains subfolder 
module 1,2 and 3 which contain header files.
#Makefile is saved in /Module/makefile

OBJS=a1.o a2.o a3.o b1.o b2.o b3.o c1.o c2.o c3.o

a1.o:a1.c
               $(CC)  -$INCLUDE -$(CFLAGS)  -I.  -I$(SRC)  -c $<
a2.o:a2.c
               $(CC)  -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<
a3.o:a3.c
               $(CC)  -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<
b1.o:b1.c
               $(CC)   -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<
b2.o:b2.c
               $(CC)  -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<
b3.o:b3.c
               $(CC)   -$INCLUDE  -$(CFLAGS)  -I.  -I$(SRC)  -c $<
c1.o:c1.c
               $(CC)   -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<
c2.o:c2.c
               $(CC)   -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<
c3.o:c3.c
               $(CC)   -$INCLUDE  -$(CFLAGS) -I.  -I$(SRC)  -c $<

all:parikshit
$(CC) -$(OBJS)  -$INCLUDE  -$(CFLAGS) -$LIBS --g -o parikshit


As far as my knowledge goes '$< ' will automatically search the mentioned 
source file in the folder mentioned by SRC .for example in this case
a1.o:a1.c
               $(CC)  -$INCLUDE -$(CFLAGS)  -I.  -I$(SRC)  -c $<
'$<' will automatically search the source file in the path mentioned by 
SRC(/Module/src) macro.
i.e.above thing will automatically search source file a1.c in /Module/src/ 
Module1/a1.c

So same thing for above source files.So why target is not being made.

Please help me .I will be highly thankful if somebody will come up with 
solution or mentioning any mistake made by me.Please reply as soon as 
possible as things are being halted for me.

Regards
Parikshat Dubey

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Re: Makefile Issue

[Brian Dessent]

Parikshat Dubey wrote:

> I have one sample make file but there are many autogenerated things inside
> it which i am unable to comprehend and understand.I want to know how
> autogenerated makefile is generated and what are the specific things in
> makefile i need to  focus on.

Please do not send your email to random addresses.  This has nothing to
do with gcc.

Each of the tools in question (autoconf, automake, libtool) have full
and detailed manuals which thoroughly explain their features.  See their
respective project pages for details.

If you just want an introduction/overview of how things fit together,
start here:
<http://www-src.lip6.fr/homepages/Alexandre.Duret-Lutz/autotools.html>.

Brian

Makefile Issue

[Parikshat Dubey]

Hi All!

I have one sample make file but there are many autogenerated things inside 
it which i am unable to comprehend and understand.I want to know how 
autogenerated makefile is generated and what are the specific things in 
makefile i need to  focus on.

I wan to know also how i can use autogenerated makefile in another makefile.

Thanks & Regards
Parikshat Dubey

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makefile issue

[Parikshat Dubey]

Hi All !

I donot know how to how to make a gtk enabled makefile.Can anyone help me 
out?I will be really thankful if anybody will help me out.

thanksandregards
parikshatdubey

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