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* shift instruction
@ 2012-06-07  6:31 naga raj
  2012-06-07  8:01 ` Ian Lance Taylor
  0 siblings, 1 reply; 3+ messages in thread
From: naga raj @ 2012-06-07  6:31 UTC (permalink / raw)
  To: gcc-help

Hi all,

   I am working on a soft-processor which has barrel-shifter as
optional i.e if barrel-shifter hardware is included then my compiler
can generate shift instructions with immediate operand if
barrel-shifter is not included than it can shift only one bit.

 Ex:  If I want to shift a register right for 24 times

    case 1: If barrel-shifter is present then it generates as below
        SHL r0,r0,#24

      case 2: Without barrel-shifter

         SHL r0,r0,#1
         SHL r0,r0,#1
         SHL r0,r0,#1
            -----
            -----
         SHL r0,r0,#1

        Compiler will generate SHL instruction for 24 times.


    Is there any chance to optimize generated code when barrel-shifter
is not used because as the immediate operand number increases it is
genereating that huge code.


Thanks in Advance,
Nagaraju

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: shift instruction
  2012-06-07  6:31 shift instruction naga raj
@ 2012-06-07  8:01 ` Ian Lance Taylor
  2012-06-08  4:59   ` naga raj
  0 siblings, 1 reply; 3+ messages in thread
From: Ian Lance Taylor @ 2012-06-07  8:01 UTC (permalink / raw)
  To: naga raj; +Cc: gcc-help

naga raj <gnuuser.raj@gmail.com> writes:

>    I am working on a soft-processor which has barrel-shifter as
> optional i.e if barrel-shifter hardware is included then my compiler
> can generate shift instructions with immediate operand if
> barrel-shifter is not included than it can shift only one bit.
>
>  Ex:  If I want to shift a register right for 24 times
>
>     case 1: If barrel-shifter is present then it generates as below
>         SHL r0,r0,#24
>
>       case 2: Without barrel-shifter
>
>          SHL r0,r0,#1
>          SHL r0,r0,#1
>          SHL r0,r0,#1
>             -----
>             -----
>          SHL r0,r0,#1
>
>         Compiler will generate SHL instruction for 24 times.
>
>
>     Is there any chance to optimize generated code when barrel-shifter
> is not used because as the immediate operand number increases it is
> genereating that huge code.

Use a predicate for your define_expand saying that ashiftMODE3 is not
available when the barrel-shifter is not available.  That should cause
gcc to generate a call to the libgcc function.

Ian

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: shift instruction
  2012-06-07  8:01 ` Ian Lance Taylor
@ 2012-06-08  4:59   ` naga raj
  0 siblings, 0 replies; 3+ messages in thread
From: naga raj @ 2012-06-08  4:59 UTC (permalink / raw)
  To: Ian Lance Taylor; +Cc: gcc-help

Thanks Ian. I will do it accordingly.

Thanks,
Nagaraju

On Thu, Jun 7, 2012 at 1:31 PM, Ian Lance Taylor <iant@google.com> wrote:
> naga raj <gnuuser.raj@gmail.com> writes:
>
>>    I am working on a soft-processor which has barrel-shifter as
>> optional i.e if barrel-shifter hardware is included then my compiler
>> can generate shift instructions with immediate operand if
>> barrel-shifter is not included than it can shift only one bit.
>>
>>  Ex:  If I want to shift a register right for 24 times
>>
>>     case 1: If barrel-shifter is present then it generates as below
>>         SHL r0,r0,#24
>>
>>       case 2: Without barrel-shifter
>>
>>          SHL r0,r0,#1
>>          SHL r0,r0,#1
>>          SHL r0,r0,#1
>>             -----
>>             -----
>>          SHL r0,r0,#1
>>
>>         Compiler will generate SHL instruction for 24 times.
>>
>>
>>     Is there any chance to optimize generated code when barrel-shifter
>> is not used because as the immediate operand number increases it is
>> genereating that huge code.
>
> Use a predicate for your define_expand saying that ashiftMODE3 is not
> available when the barrel-shifter is not available.  That should cause
> gcc to generate a call to the libgcc function.
>
> Ian

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2012-06-08  4:59 UTC | newest]

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2012-06-07  6:31 shift instruction naga raj
2012-06-07  8:01 ` Ian Lance Taylor
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