[PATCH, testsuite, ARM] Skip combine-cmp-shift.c and unsined-extend-1.c for Thumb1

[PATCH, testsuite, ARM] Skip combine-cmp-shift.c and unsined-extend-1.c for Thumb1

[Zhenqiang Chen]

Hi,

For combine-cmp-shift.c, Thumb1 does not have cmp and shift instruction.
For unsigned-extend-1.c, it bases on conditional execution to optimize uxtb.
But this is not for Thumb1.

The patch skips the final check when arm_thumb1_ok.

OK for trunk?

Thanks!
-Zhenqiang

testsuite/ChangeLog:
2014-11-03  Zhenqiang Chen  <zhenqiang.chen@arm.com>

	* gcc.target/arm/combine-cmp-shift.c: Skip arm_thumb1_ok.
	* gcc.target/arm/unsined-extend-1.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
index a64f20e..6291b06 100644
--- a/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
+++ b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } {
"-march=armv7-a" } } */
 /* { dg-options "-O2 -mcpu=cortex-a8" }  */
-/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */
+/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" {
target { ! arm_thumb1_ok } } } } */
 
 typedef int SItype __attribute__ ((mode (SI)));
 typedef int DItype __attribute__ ((mode (DI)));
diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
b/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
index 3b4ab04..ea90548 100644
--- a/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
+++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
@@ -6,4 +6,4 @@ unsigned char foo (unsigned char c)
   return (c >= '0') && (c <= '9');
 }
 
-/* { dg-final { scan-assembler-not "uxtb" } } */
+/* { dg-final { scan-assembler-not "uxtb" { target { ! arm_thumb1_ok } } }
} */