* [nvptx PATCH] Update nvptx's bitrev<mode>2 pattern to use BITREVERSE rtx.
@ 2023-06-07 23:09 Roger Sayle
2023-11-15 14:33 ` Thomas Schwinge
0 siblings, 1 reply; 2+ messages in thread
From: Roger Sayle @ 2023-06-07 23:09 UTC (permalink / raw)
To: gcc-patches
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This minor tweak to the nvptx backend switches the representation of
of the brev instruction from an UNSPEC to instead use the new BITREVERSE
rtx. This allows various RTL optimizations including evaluation (constant
folding) of integer constant arguments at compile-time.
This patch has been tested on nvptx-none with make and make -k check
with no new failures. Ok for mainline?
2023-06-07 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/nvptx/nvptx.md (UNSPEC_BITREV): Delete.
(bitrev<mode>2): Represent using bitreverse.
Thanks in advance,
Roger
--
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diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index 1bb9304..7a7c994 100644
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -34,8 +34,6 @@
UNSPEC_FPINT_CEIL
UNSPEC_FPINT_NEARBYINT
- UNSPEC_BITREV
-
UNSPEC_ALLOCA
UNSPEC_SET_SOFTSTACK
@@ -636,8 +634,7 @@
(define_insn "bitrev<mode>2"
[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
- (unspec:SDIM [(match_operand:SDIM 1 "nvptx_register_operand" "R")]
- UNSPEC_BITREV))]
+ (bitreverse:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")))]
""
"%.\\tbrev.b%T0\\t%0, %1;")
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [nvptx PATCH] Update nvptx's bitrev<mode>2 pattern to use BITREVERSE rtx.
2023-06-07 23:09 [nvptx PATCH] Update nvptx's bitrev<mode>2 pattern to use BITREVERSE rtx Roger Sayle
@ 2023-11-15 14:33 ` Thomas Schwinge
0 siblings, 0 replies; 2+ messages in thread
From: Thomas Schwinge @ 2023-11-15 14:33 UTC (permalink / raw)
To: Roger Sayle, gcc-patches; +Cc: Tom de Vries
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Hi!
On 2023-06-08T00:09:00+0100, "Roger Sayle" <roger@nextmovesoftware.com> wrote:
> This minor tweak to the nvptx backend switches the representation of
> of the brev instruction from an UNSPEC to instead use the new BITREVERSE
> rtx.
ACK.
> This allows various RTL optimizations including evaluation (constant
> folding) of integer constant arguments at compile-time.
..., which we're then observing via
commit 61c45c055a5ccfc59463c21ab057dece822d973c
"nvptx: Extend 'brev' test cases" that I just pushed;
<https://inbox.sourceware.org/87a5rfum3v.fsf@euler.schwinge.homeip.net>
"nvptx: Extend 'brev' test cases".
> This patch has been tested on nvptx-none with make and make -k check
> with no new failures. Ok for mainline?
I've thus updated the test cases for these changes here, and pushed to
master branch commit 75c20a99b3a242121eef8a532f5224c00c471b56
"Update nvptx's bitrev<mode>2 pattern to use BITREVERSE rtx.", see
attached.
Grüße
Thomas
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From 75c20a99b3a242121eef8a532f5224c00c471b56 Mon Sep 17 00:00:00 2001
From: Roger Sayle <roger@nextmovesoftware.com>
Date: Thu, 8 Jun 2023 00:09:00 +0100
Subject: [PATCH] Update nvptx's bitrev<mode>2 pattern to use BITREVERSE rtx.
This minor tweak to the nvptx backend switches the representation of
of the brev instruction from an UNSPEC to instead use the new BITREVERSE
rtx. This allows various RTL optimizations including evaluation (constant
folding) of integer constant arguments at compile-time.
gcc/
* config/nvptx/nvptx.md (UNSPEC_BITREV): Delete.
(bitrev<mode>2): Represent using bitreverse.
gcc/testsuite/
* gcc.target/nvptx/brev-2-O2.c: Adjust.
* gcc.target/nvptx/brevll-2-O2.c: Likewise.
Co-authored-by: Thomas Schwinge <thomas@codesourcery.com>
---
gcc/config/nvptx/nvptx.md | 5 +---
gcc/testsuite/gcc.target/nvptx/brev-2-O2.c | 25 ++------------------
gcc/testsuite/gcc.target/nvptx/brevll-2-O2.c | 25 ++------------------
3 files changed, 5 insertions(+), 50 deletions(-)
diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index 1bb93045403..7a7c9948f45 100644
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -34,8 +34,6 @@
UNSPEC_FPINT_CEIL
UNSPEC_FPINT_NEARBYINT
- UNSPEC_BITREV
-
UNSPEC_ALLOCA
UNSPEC_SET_SOFTSTACK
@@ -636,8 +634,7 @@
(define_insn "bitrev<mode>2"
[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
- (unspec:SDIM [(match_operand:SDIM 1 "nvptx_register_operand" "R")]
- UNSPEC_BITREV))]
+ (bitreverse:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")))]
""
"%.\\tbrev.b%T0\\t%0, %1;")
diff --git a/gcc/testsuite/gcc.target/nvptx/brev-2-O2.c b/gcc/testsuite/gcc.target/nvptx/brev-2-O2.c
index e35052208d0..c707a87f356 100644
--- a/gcc/testsuite/gcc.target/nvptx/brev-2-O2.c
+++ b/gcc/testsuite/gcc.target/nvptx/brev-2-O2.c
@@ -1,7 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2" } */
/* { dg-additional-options -save-temps } */
-/* { dg-final { check-function-bodies {**} {} } } */
inline __attribute__((always_inline))
unsigned int bitreverse32(unsigned int x)
@@ -96,26 +95,6 @@ int main(void)
return 0;
}
-/*
-** main:
-** ...
-** mov\.u32 (%r[0-9]+), 0;
-** brev\.b32 (%r[0-9]+), \1;
-** setp\.[^.]+\.u32 %r[0-9]+, \2, 0;
-** ...
-** mov\.u32 (%r[0-9]+), -1;
-** brev\.b32 (%r[0-9]+), \3;
-** setp\.[^.]+\.u32 %r[0-9]+, \4, -1;
-** ...
-** mov\.u32 (%r[0-9]+), 1;
-** brev\.b32 (%r[0-9]+), \5;
-** setp\.[^.]+\.u32 %r[0-9]+, \6, -2147483648;
-** ...
-** mov\.u32 (%r[0-9]+), 2;
-** brev\.b32 (%r[0-9]+), \7;
-** setp\.[^.]+\.u32 %r[0-9]+, \8, 1073741824;
-** ...
-*/
-/* { dg-final { scan-assembler-times {\tbrev\.b32\t} 40 } } */
-/* { dg-final { scan-assembler {\mabort\M} } } */
+/* { dg-final { scan-assembler-not {\tbrev\.b32\t} } } */
+/* { dg-final { scan-assembler-not {\mabort\M} } } */
diff --git a/gcc/testsuite/gcc.target/nvptx/brevll-2-O2.c b/gcc/testsuite/gcc.target/nvptx/brevll-2-O2.c
index cbfda1b9601..c89be9627f8 100644
--- a/gcc/testsuite/gcc.target/nvptx/brevll-2-O2.c
+++ b/gcc/testsuite/gcc.target/nvptx/brevll-2-O2.c
@@ -1,7 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2" } */
/* { dg-additional-options -save-temps } */
-/* { dg-final { check-function-bodies {**} {} } } */
inline __attribute__((always_inline))
unsigned long long bitreverse64(unsigned long long x)
@@ -156,26 +155,6 @@ int main(void)
return 0;
}
-/*
-** main:
-** ...
-** mov\.u64 (%r[0-9]+), 0;
-** brev\.b64 (%r[0-9]+), \1;
-** setp\.[^.]+\.u64 %r[0-9]+, \2, 0;
-** ...
-** mov\.u64 (%r[0-9]+), -1;
-** brev\.b64 (%r[0-9]+), \3;
-** setp\.[^.]+\.u64 %r[0-9]+, \4, -1;
-** ...
-** mov\.u64 (%r[0-9]+), 1;
-** brev\.b64 (%r[0-9]+), \5;
-** setp\.[^.]+\.u64 %r[0-9]+, \6, -9223372036854775808;
-** ...
-** mov\.u64 (%r[0-9]+), 2;
-** brev\.b64 (%r[0-9]+), \7;
-** setp\.[^.]+\.u64 %r[0-9]+, \8, 4611686018427387904;
-** ...
-*/
-/* { dg-final { scan-assembler-times {\tbrev\.b64\t} 70 } } */
-/* { dg-final { scan-assembler {\mabort\M} } } */
+/* { dg-final { scan-assembler-not {\tbrev\.b64\t} } } */
+/* { dg-final { scan-assembler-not {\mabort\M} } } */
--
2.34.1
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