From: "Jie Mei" <jie.mei@oss.cipunited.com>
To: <gcc-patches@gcc.gnu.org>
Cc: "YunQiang Su" <yunqiang.su@cipunited.com>,
"Maciej W . Rozycki" <macro@orcam.me.uk>
Subject: [PATCH v3 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2
Date: Wed, 24 May 2023 17:41:21 +0800 [thread overview]
Message-ID: <0ac6b0c13cfd5465a6ce38a5f04fc172e4ffb7da.1684918169.git.jie.mei@oss.cipunited.com> (raw)
In-Reply-To: <cover.1684918168.git.jie.mei@oss.cipunited.com>
[-- Attachment #1: Type: text/plain, Size: 2005 bytes --]
The MIPS16e2 ASE has PREF, LL and SC instructions,
they use 9 bits immediate, like mips32r6.
The MIPS32 PRE-R6 uses 16 bits immediate.
gcc/ChangeLog:
* config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
for ISA_HAS_MIPS16E2.
(ISA_HAS_SYNC): Same as above.
(ISA_HAS_LL_SC): Same as above.
---
gcc/config/mips/mips.h | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b6c100060da..f50b279af33 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1247,7 +1247,8 @@ struct mips_cpu_info {
&& !TARGET_MIPS16)
/* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
-#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
+#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \
+ || ISA_HAS_MIPS16E2)
/* ISA has data indexed prefetch instructions. This controls use of
'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
@@ -1340,7 +1341,8 @@ struct mips_cpu_info {
#define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
/* ISA includes sync. */
-#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16)
+#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) \
+ && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
#define GENERATE_SYNC \
(target_flags_explicit & MASK_LLSC \
? TARGET_LLSC && !TARGET_MIPS16 \
@@ -1349,7 +1351,8 @@ struct mips_cpu_info {
/* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
instructions. */
-#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
+#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 \
+ && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
#define GENERATE_LL_SC \
(target_flags_explicit & MASK_LLSC \
? TARGET_LLSC && !TARGET_MIPS16 \
--
2.40.1
next prev parent reply other threads:[~2023-05-24 9:41 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-24 9:41 [PATCH v3 0/9] MIPS: Add MIPS16e2 ASE instrucions Jie Mei
2023-05-24 9:41 ` [PATCH v3 1/9] MIPS: Add basic support for mips16e2 Jie Mei
2023-05-24 9:41 ` [PATCH v3 2/9] MIPS: Add MOVx instructions " Jie Mei
2023-05-24 9:41 ` [PATCH v3 3/9] MIPS: Add instruction about global pointer register " Jie Mei
2023-05-24 9:41 ` [PATCH v3 4/9] MIPS: Add bitwise instructions " Jie Mei
2023-05-24 9:41 ` [PATCH v3 5/9] MIPS: Add LUI instruction " Jie Mei
2023-05-24 9:41 ` [PATCH v3 6/9] MIPS: Add load/store word left/right instructions " Jie Mei
2023-05-24 9:41 ` Jie Mei [this message]
2023-05-24 9:41 ` [PATCH v3 8/9] MIPS: Add CACHE instruction " Jie Mei
2023-05-24 9:41 ` [PATCH v3 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions Jie Mei
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