From: Andrew Stubbs <ams@codesourcery.com>
To: <gcc-patches@gcc.gnu.org>
Subject: [committed 2/6] amdgcn: Resolve insn conditions at compile time
Date: Tue, 11 Oct 2022 12:02:04 +0100 [thread overview]
Message-ID: <0d8753cf30486c4e7fb07455b7cae49aa812c6a4.1665485382.git.ams@codesourcery.com> (raw)
In-Reply-To: <cover.1665485382.git.ams@codesourcery.com>
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GET_MODE_NUNITS isn't a compile time constant, so we end up with many
impossible insns in the machine description. Adding MODE_VF allows the insns
to be eliminated completely.
gcc/ChangeLog:
* config/gcn/gcn-valu.md
(<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): Use MODE_VF.
(<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): Likewise.
* config/gcn/gcn.h (MODE_VF): New macro.
---
gcc/config/gcn/gcn-valu.md | 10 ++++++----
gcc/config/gcn/gcn.h | 24 ++++++++++++++++++++++++
2 files changed, 30 insertions(+), 4 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0002-amdgcn-Resolve-insn-conditions-at-compile-time.patch --]
[-- Type: text/x-patch; name="0002-amdgcn-Resolve-insn-conditions-at-compile-time.patch", Size: 2704 bytes --]
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 52d2fcb880a..c7be2361164 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2873,8 +2873,9 @@ (define_insn "<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>"
[(set (match_operand:VCVT_FMODE 0 "register_operand" "= v")
(cvt_op:VCVT_FMODE
(match_operand:VCVT_MODE 1 "gcn_alu_operand" "vSvB")))]
- "gcn_valid_cvt_p (<VCVT_MODE:MODE>mode, <VCVT_FMODE:MODE>mode,
- <cvt_name>_cvt)"
+ "MODE_VF (<VCVT_MODE:MODE>mode) == MODE_VF (<VCVT_FMODE:MODE>mode)
+ && gcn_valid_cvt_p (<VCVT_MODE:MODE>mode, <VCVT_FMODE:MODE>mode,
+ <cvt_name>_cvt)"
"v_cvt<cvt_operands>\t%0, %1"
[(set_attr "type" "vop1")
(set_attr "length" "8")])
@@ -2883,8 +2884,9 @@ (define_insn "<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>"
[(set (match_operand:VCVT_IMODE 0 "register_operand" "= v")
(cvt_op:VCVT_IMODE
(match_operand:VCVT_FMODE 1 "gcn_alu_operand" "vSvB")))]
- "gcn_valid_cvt_p (<VCVT_FMODE:MODE>mode, <VCVT_IMODE:MODE>mode,
- <cvt_name>_cvt)"
+ "MODE_VF (<VCVT_IMODE:MODE>mode) == MODE_VF (<VCVT_FMODE:MODE>mode)
+ && gcn_valid_cvt_p (<VCVT_FMODE:MODE>mode, <VCVT_IMODE:MODE>mode,
+ <cvt_name>_cvt)"
"v_cvt<cvt_operands>\t%0, %1"
[(set_attr "type" "vop1")
(set_attr "length" "8")])
diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h
index 318256c4a7a..38f7212db59 100644
--- a/gcc/config/gcn/gcn.h
+++ b/gcc/config/gcn/gcn.h
@@ -678,3 +678,27 @@ enum gcn_builtin_codes
/* Trampolines */
#define TRAMPOLINE_SIZE 36
#define TRAMPOLINE_ALIGNMENT 64
+
+/* MD Optimization.
+ The following are intended to be obviously constant at compile time to
+ allow genconditions to eliminate bad patterns at compile time. */
+#define MODE_VF(M) \
+ ((M == V64QImode || M == V64HImode || M == V64HFmode || M == V64SImode \
+ || M == V64SFmode || M == V64DImode || M == V64DFmode) \
+ ? 64 \
+ : (M == V32QImode || M == V32HImode || M == V32HFmode || M == V32SImode \
+ || M == V32SFmode || M == V32DImode || M == V32DFmode) \
+ ? 32 \
+ : (M == V16QImode || M == V16HImode || M == V16HFmode || M == V16SImode \
+ || M == V16SFmode || M == V16DImode || M == V16DFmode) \
+ ? 16 \
+ : (M == V8QImode || M == V8HImode || M == V8HFmode || M == V8SImode \
+ || M == V8SFmode || M == V8DImode || M == V8DFmode) \
+ ? 8 \
+ : (M == V4QImode || M == V4HImode || M == V4HFmode || M == V4SImode \
+ || M == V4SFmode || M == V4DImode || M == V4DFmode) \
+ ? 4 \
+ : (M == V2QImode || M == V2HImode || M == V2HFmode || M == V2SImode \
+ || M == V2SFmode || M == V2DImode || M == V2DFmode) \
+ ? 2 \
+ : 1)
next prev parent reply other threads:[~2022-10-11 11:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-11 11:02 [committed 0/6] amdgcn: Add V32, V16, V8, V4, and V2 vectors Andrew Stubbs
2022-10-11 11:02 ` [committed 1/6] amdgcn: add multiple vector sizes Andrew Stubbs
2022-10-17 12:26 ` GCN: Restore build with GCC 4.8 (was: [committed 1/6] amdgcn: add multiple vector sizes) Thomas Schwinge
2022-10-11 11:02 ` Andrew Stubbs [this message]
2022-10-11 11:02 ` [committed 3/6] amdgcn: Add vec_extract for partial vectors Andrew Stubbs
2022-10-11 11:02 ` [committed 4/6] amdgcn: vec_init for multiple vector sizes Andrew Stubbs
2022-10-11 11:02 ` [committed 5/6] amdgcn: Add vector integer negate insn Andrew Stubbs
2022-10-11 11:02 ` [committed 6/6] amdgcn: vector testsuite tweaks Andrew Stubbs
2022-10-28 7:46 ` Thomas Schwinge
2022-10-28 8:38 ` Stubbs, Andrew
2022-10-28 9:00 ` Thomas Schwinge
2022-10-11 11:29 ` [committed 0/6] amdgcn: Add V32, V16, V8, V4, and V2 vectors Richard Biener
2022-10-11 11:53 ` Andrew Stubbs
2022-10-11 11:58 ` Richard Biener
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