[PATCH] [Patch ARM] Fix PR target/49335 .

[PATCH] [Patch ARM] Fix PR target/49335 .

[Ramana Radhakrishnan]

Hi,

This fixes an issue with PR target/49335 where we have a situation
where the sp register is being used as a source operand in the rsb
instruction in the shifted immediate form in Thumb2 i.e.

    rsb ip, sp, ip lsl #2

The only valid instructions in Thumb2 that can do this are the
add and the sub instruction.

I have not been able to convert the original C++ testcase into
an equivalent C testcase neither was I able to generate the
rsb instruction using the sp with a C only testcase. What's the thought
on putting a C++ testcase in gcc.target and checking for rsb with sp

Tested on v7-a cross in both ARM and Thumb configurations on qemu
with no regressions for C, C++ and Fortran.

Ok (and to backport to 4.6 branch) ?

cheers
Ramana

2011-06-09  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/49335
	* config/arm/predicates.md (add_operator): New.
	* config/arm/arm.md ("*arith_shiftsi"): Fix for SP reg usage
	in Thumb2.
---
 gcc/config/arm/arm.md        |   22 +++++++++++++++-------
 gcc/config/arm/predicates.md |    3 +++
 2 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4e84826..ecf3777 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8620,18 +8620,22 @@
 ;; Patterns to allow combination of arithmetic, cond code and shifts
 
 (define_insn "*arith_shiftsi"
-  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+  [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
         (match_operator:SI 1 "shiftable_operator"
           [(match_operator:SI 3 "shift_operator"
-             [(match_operand:SI 4 "s_register_operand" "r,r")
-              (match_operand:SI 5 "shift_amount_operand" "M,r")])
-           (match_operand:SI 2 "s_register_operand" "rk,rk")]))]
+             [(match_operand:SI 4 "s_register_operand" "r,r,r,r")
+              (match_operand:SI 5 "shift_amount_operand" "M,M,M,r")])
+           (match_operand:SI 2 "s_register_operand" "rk,rk,r,rk")]))]
   "TARGET_32BIT"
   "%i1%?\\t%0, %2, %4%S3"
   [(set_attr "predicable" "yes")
    (set_attr "shift" "4")
-   (set_attr "arch" "32,a")
-   ;; We have to make sure to disable the second alternative if
+   (set_attr "arch" "a,t2,t2,a")
+   ;; Thumb2 doesn't allow the stack pointer to be used for 
+   ;; operand1 for all operations other than add and sub. In this case 
+   ;; the minus operation is a candidate for an rsub and hence needs
+   ;; to be disabled.
+   ;; We have to make sure to disable the fourth alternative if
    ;; the shift_operator is MULT, since otherwise the insn will
    ;; also match a multiply_accumulate pattern and validate_change
    ;; will allow a replacement of the constant with a register
@@ -8639,9 +8643,13 @@
    (set_attr_alternative "insn_enabled"
 			 [(const_string "yes")
 			  (if_then_else
+			   (match_operand:SI 1 "add_operator" "")
+			   (const_string "yes") (const_string "no"))
+			  (const_string "yes")
+			  (if_then_else
 			   (match_operand:SI 3 "mult_operator" "")
 			   (const_string "no") (const_string "yes"))])
-   (set_attr "type" "alu_shift,alu_shift_reg")])
+   (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")])
 
 (define_split
   [(set (match_operand:SI 0 "s_register_operand" "")
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 891a974..f4dda23 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -687,3 +687,6 @@
 (define_special_predicate "neon_struct_operand"
   (and (match_code "mem")
        (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
+
+(define_special_predicate "add_operator"
+  (match_code "plus"))
-- 
1.7.4.1