[PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Lehua Ding]

Hi,

This patch does several things:
  1. Adds the missed checking of tuple vector mode
  2. Extend the scope of checking to all vector types, previously it
     was only for scalable vector types.
  3. Simplify the logic of determining code of vector type which will lower to
     vector tmode  code

Best,
Lehua

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete.
	(riscv_arg_has_vector): Simplify.
	(riscv_pass_in_vector_p): Adjust warning message.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Add -Wno-psabi option.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto.
	* gcc.target/riscv/rvv/base/pr110119-1.c: Ditto.
	* gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
	* gcc.target/riscv/vector-abi-1.c: Ditto.
	* gcc.target/riscv/vector-abi-2.c: Ditto.
	* gcc.target/riscv/vector-abi-3.c: Ditto.
	* gcc.target/riscv/vector-abi-4.c: Ditto.
	* gcc.target/riscv/vector-abi-5.c: Ditto.
	* gcc.target/riscv/vector-abi-6.c: Ditto.
	* gcc.target/riscv/vector-abi-7.c: New test.
	* gcc.target/riscv/vector-abi-8.c: New test.
	* gcc.target/riscv/vector-abi-9.c: New test.

---
 gcc/config/riscv/riscv.cc                     | 53 ++++++-------------
 .../riscv/rvv/autovec/fixed-vlmax-1.c         |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-1.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-2.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-3.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-4.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-5.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-6.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-7.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-1.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-2.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-3.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-4.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-5.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-6.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-7.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm-1.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm-2.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm-3.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm-4.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm-5.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm-6.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm-7.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-1.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-2.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-3.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-4.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-5.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-6.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-7.c  |  2 +-
 .../gcc.target/riscv/rvv/base/pr110119-1.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr110119-2.c    |  2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  9 +++-
 gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-7.c | 14 +++++
 gcc/testsuite/gcc.target/riscv/vector-abi-8.c | 14 +++++
 gcc/testsuite/gcc.target/riscv/vector-abi-9.c | 16 ++++++
 41 files changed, 104 insertions(+), 74 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-9.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e5ae4e81b7a5..d1ff02c7b367 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3795,31 +3795,22 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
-/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
-   intrinsic vector type.  Because we can't get the decl for the params.  */
-
-static bool
-riscv_scalable_vector_type_p (const_tree type)
-{
-  tree size = TYPE_SIZE (type);
-  if (size && TREE_CODE (size) == INTEGER_CST)
-    return false;
-
-  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
-  return true;
-}
+/* Return true if a vector type is included in the type TYPE.  */
 
 static bool
 riscv_arg_has_vector (const_tree type)
 {
-  bool is_vector = false;
+  if (riscv_v_ext_mode_p (TYPE_MODE (type)))
+    return true;
+
+  if (!COMPLETE_TYPE_P (type))
+    return false;
 
   switch (TREE_CODE (type))
     {
     case RECORD_TYPE:
-      if (!COMPLETE_TYPE_P (type))
-	break;
-
+      /* If it is a record, it is further determined whether its fileds have
+         vector type.  */
       for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
 	if (TREE_CODE (f) == FIELD_DECL)
 	  {
@@ -3827,25 +3818,15 @@ riscv_arg_has_vector (const_tree type)
 	    if (!TYPE_P (field_type))
 	      break;
 
-	    /* Ignore it if it's fixed length vector.  */
-	    if (VECTOR_TYPE_P (field_type))
-	      is_vector = riscv_scalable_vector_type_p (field_type);
-	    else
-	      is_vector = riscv_arg_has_vector (field_type);
+	    if (riscv_arg_has_vector (field_type))
+	      return true;
 	  }
-
-      break;
-
-    case VECTOR_TYPE:
-      is_vector = riscv_scalable_vector_type_p (type);
-      break;
-
-    default:
-      is_vector = false;
       break;
+    case ARRAY_TYPE:
+      return riscv_arg_has_vector (TREE_TYPE (type));
     }
 
-  return is_vector;
+  return false;
 }
 
 /* Pass the type to check whether it's a vector type or contains vector type.
@@ -3856,11 +3837,11 @@ riscv_pass_in_vector_p (const_tree type)
 {
   static int warned = 0;
 
-  if (type && riscv_arg_has_vector (type) && !warned)
+  if (type && riscv_v_ext_mode_p (TYPE_MODE (type)) && !warned)
     {
-      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
-	       "experimental stage and may changes in the upcoming version of "
-	       "GCC.");
+      warning (OPT_Wpsabi,
+	       "ABI for the vector type is currently in experimental stage and "
+	       "may changes in the upcoming version of GCC.");
       warned = 1;
     }
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
index 09e8396936ef..61eac38e541f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
index efeb23e9719b..3e3ecd1ef568 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
index 35b2aa8aee99..f07b65801a29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
index 957d5b26fdce..57bf8fae6861 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
index 398d0dcc6492..8bc29c3df853 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
index 4d1b9e29b7db..f6140fbc3958 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
index 43acea6c345c..7ab4bca7dea0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
index 2f38c3d13f54..a50102678d2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
index 7449f63583c8..d6e8248ba0b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
index 248a30433a5d..08506e336d80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
index a587dd45eb17..ff92c3926e4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
index 18dedb0f77de..86a3f2df7b37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
index 61dbd5b4f2b6..a64f82fbab7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
index da7c462e0c37..6193d2a6c525 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
index 7aaa6b37d521..267c1ac77285 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
index 58c2cd8ce23f..b361a04836ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
index d88b6461da54..9e9123a6ceff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
index 110df490c6e3..0cefb2416475 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index aa328810c305..9df69a0cc2c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
index 7117a492dc73..e03f8e1ad51b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
index 67b2e6f680ee..c74ad03935e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
index 0ac982872544..46c4a71256d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
index cb216a9543c9..8fe80e6d54c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
index 1b51b315ad12..04906d3c4fd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
index 4cae7f4f1a57..f5e9f9e59198 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
index e60b19fab68e..8460491b8106 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
index b61990915b09..5394dec2045c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
index b23df90f0acf..cee7efc3aa33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
index d935d36bf69b..49b25830b8d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */
 
 #include "perm-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
index f16502bcfeec..c5d9b1538cde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
index b233ff1e9040..958d1addb055 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint.h>
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
index 969f14277a47..114ee6de483e 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -4,7 +4,7 @@
 #include "riscv_vector.h"
 
 void
-fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
index 63d97d30fc59..0b24ccb83122 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -5,7 +5,7 @@
 #include "riscv_vector.h"
 
 vint32m1_t
-fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
index 90ece60cc6fc..844a5db4027e 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -4,7 +4,7 @@
 #include "riscv_vector.h"
 
 vint32m1_t*
-fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
index ecf6d4cc26bc..a5dc2dffaac6 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -6,7 +6,7 @@
 typedef int v4si __attribute__ ((vector_size (16)));
 
 v4si
-fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+fun (v4si a) {  return a; }  /* { dg-bogus "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
index 6053e0783b6d..9dc69518b5d6 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -2,10 +2,15 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d" } */
 
 typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; v4si b; };
+struct A { int a; int b; };
+
+void foo (int b);
 
 void
-fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+fun (struct A a) {
+
+        foo (a.b);
+} /* { dg-bogus "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
index 63bc4a898057..3a65f2c60ab9 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -12,7 +12,7 @@ foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
     vl = __riscv_vsetvlmax_e16mf2();
   for (size_t i = 0; i < n; i += 1)
     {
-      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
       vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
       vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
       __riscv_vse32_v_i32m1(out, c, vl);
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
new file mode 100644
index 000000000000..2795fd4f9fb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1x3_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
new file mode 100644
index 000000000000..9cf68d4da9cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1x3_t*
+fun (vint32m1x3_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1x3_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-9.c b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
new file mode 100644
index 000000000000..b5f130f0caf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
-- 
2.36.3

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[钟居哲]

[-- Attachment #1: Type: text/plain, Size: 31349 bytes --]

Thanks for cleaning up codes for future's ABI support patch.
Let's wait for Jeff or Robin comments.

Thanks.


juzhe.zhong@rivai.ai
 
From: Lehua Ding
Date: 2023-06-18 19:41
To: gcc-patches
CC: juzhe.zhong; yanzhang.wang; kito.cheng; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
Hi,
 
This patch does several things:
  1. Adds the missed checking of tuple vector mode
  2. Extend the scope of checking to all vector types, previously it
     was only for scalable vector types.
  3. Simplify the logic of determining code of vector type which will lower to
     vector tmode  code
 
Best,
Lehua
 
gcc/ChangeLog:
 
* config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete.
(riscv_arg_has_vector): Simplify.
(riscv_pass_in_vector_p): Adjust warning message.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Add -Wno-psabi option.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto.
* gcc.target/riscv/rvv/base/pr110119-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
* gcc.target/riscv/vector-abi-1.c: Ditto.
* gcc.target/riscv/vector-abi-2.c: Ditto.
* gcc.target/riscv/vector-abi-3.c: Ditto.
* gcc.target/riscv/vector-abi-4.c: Ditto.
* gcc.target/riscv/vector-abi-5.c: Ditto.
* gcc.target/riscv/vector-abi-6.c: Ditto.
* gcc.target/riscv/vector-abi-7.c: New test.
* gcc.target/riscv/vector-abi-8.c: New test.
* gcc.target/riscv/vector-abi-9.c: New test.
 
---
gcc/config/riscv/riscv.cc                     | 53 ++++++-------------
.../riscv/rvv/autovec/fixed-vlmax-1.c         |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-1.c     |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-2.c     |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-3.c     |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-4.c     |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-5.c     |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-6.c     |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-7.c     |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-1.c |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-2.c |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-3.c |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-4.c |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-5.c |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-6.c |  2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-7.c |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-1.c      |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-2.c      |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-3.c      |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-4.c      |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-5.c      |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-6.c      |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-7.c      |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-1.c  |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-2.c  |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-3.c  |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-4.c  |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-5.c  |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-6.c  |  2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-7.c  |  2 +-
.../gcc.target/riscv/rvv/base/pr110119-1.c    |  2 +-
.../gcc.target/riscv/rvv/base/pr110119-2.c    |  2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  9 +++-
gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-7.c | 14 +++++
gcc/testsuite/gcc.target/riscv/vector-abi-8.c | 14 +++++
gcc/testsuite/gcc.target/riscv/vector-abi-9.c | 16 ++++++
41 files changed, 104 insertions(+), 74 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-9.c
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e5ae4e81b7a5..d1ff02c7b367 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3795,31 +3795,22 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
   GEN_INT (offset2))));
}
-/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
-   intrinsic vector type.  Because we can't get the decl for the params.  */
-
-static bool
-riscv_scalable_vector_type_p (const_tree type)
-{
-  tree size = TYPE_SIZE (type);
-  if (size && TREE_CODE (size) == INTEGER_CST)
-    return false;
-
-  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
-  return true;
-}
+/* Return true if a vector type is included in the type TYPE.  */
static bool
riscv_arg_has_vector (const_tree type)
{
-  bool is_vector = false;
+  if (riscv_v_ext_mode_p (TYPE_MODE (type)))
+    return true;
+
+  if (!COMPLETE_TYPE_P (type))
+    return false;
   switch (TREE_CODE (type))
     {
     case RECORD_TYPE:
-      if (!COMPLETE_TYPE_P (type))
- break;
-
+      /* If it is a record, it is further determined whether its fileds have
+         vector type.  */
       for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
if (TREE_CODE (f) == FIELD_DECL)
  {
@@ -3827,25 +3818,15 @@ riscv_arg_has_vector (const_tree type)
    if (!TYPE_P (field_type))
      break;
-     /* Ignore it if it's fixed length vector.  */
-     if (VECTOR_TYPE_P (field_type))
-       is_vector = riscv_scalable_vector_type_p (field_type);
-     else
-       is_vector = riscv_arg_has_vector (field_type);
+     if (riscv_arg_has_vector (field_type))
+       return true;
  }
-
-      break;
-
-    case VECTOR_TYPE:
-      is_vector = riscv_scalable_vector_type_p (type);
-      break;
-
-    default:
-      is_vector = false;
       break;
+    case ARRAY_TYPE:
+      return riscv_arg_has_vector (TREE_TYPE (type));
     }
-  return is_vector;
+  return false;
}
/* Pass the type to check whether it's a vector type or contains vector type.
@@ -3856,11 +3837,11 @@ riscv_pass_in_vector_p (const_tree type)
{
   static int warned = 0;
-  if (type && riscv_arg_has_vector (type) && !warned)
+  if (type && riscv_v_ext_mode_p (TYPE_MODE (type)) && !warned)
     {
-      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
-        "experimental stage and may changes in the upcoming version of "
-        "GCC.");
+      warning (OPT_Wpsabi,
+        "ABI for the vector type is currently in experimental stage and "
+        "may changes in the upcoming version of GCC.");
       warned = 1;
     }
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
index 09e8396936ef..61eac38e541f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
index efeb23e9719b..3e3ecd1ef568 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
index 35b2aa8aee99..f07b65801a29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
index 957d5b26fdce..57bf8fae6861 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
index 398d0dcc6492..8bc29c3df853 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
index 4d1b9e29b7db..f6140fbc3958 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
index 43acea6c345c..7ab4bca7dea0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
index 2f38c3d13f54..a50102678d2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
index 7449f63583c8..d6e8248ba0b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
index 248a30433a5d..08506e336d80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
index a587dd45eb17..ff92c3926e4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
index 18dedb0f77de..86a3f2df7b37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
index 61dbd5b4f2b6..a64f82fbab7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
index da7c462e0c37..6193d2a6c525 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
index 7aaa6b37d521..267c1ac77285 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
index 58c2cd8ce23f..b361a04836ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
index d88b6461da54..9e9123a6ceff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
index 110df490c6e3..0cefb2416475 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index aa328810c305..9df69a0cc2c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
index 7117a492dc73..e03f8e1ad51b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
index 67b2e6f680ee..c74ad03935e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
index 0ac982872544..46c4a71256d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
index cb216a9543c9..8fe80e6d54c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
index 1b51b315ad12..04906d3c4fd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
index 4cae7f4f1a57..f5e9f9e59198 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
index e60b19fab68e..8460491b8106 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
index b61990915b09..5394dec2045c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
index b23df90f0acf..cee7efc3aa33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
index d935d36bf69b..49b25830b8d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */
#include "perm-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
index f16502bcfeec..c5d9b1538cde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
index b233ff1e9040..958d1addb055 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint.h>
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
index 969f14277a47..114ee6de483e 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -4,7 +4,7 @@
#include "riscv_vector.h"
void
-fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
index 63d97d30fc59..0b24ccb83122 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -5,7 +5,7 @@
#include "riscv_vector.h"
vint32m1_t
-fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
index 90ece60cc6fc..844a5db4027e 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -4,7 +4,7 @@
#include "riscv_vector.h"
vint32m1_t*
-fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
index ecf6d4cc26bc..a5dc2dffaac6 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -6,7 +6,7 @@
typedef int v4si __attribute__ ((vector_size (16)));
v4si
-fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+fun (v4si a) {  return a; }  /* { dg-bogus "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
index 6053e0783b6d..9dc69518b5d6 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -2,10 +2,15 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; v4si b; };
+struct A { int a; int b; };
+
+void foo (int b);
void
-fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+fun (struct A a) {
+
+        foo (a.b);
+} /* { dg-bogus "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
index 63bc4a898057..3a65f2c60ab9 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -12,7 +12,7 @@ foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
     vl = __riscv_vsetvlmax_e16mf2();
   for (size_t i = 0; i < n; i += 1)
     {
-      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
       vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
       vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
       __riscv_vse32_v_i32m1(out, c, vl);
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
new file mode 100644
index 000000000000..2795fd4f9fb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1x3_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
new file mode 100644
index 000000000000..9cf68d4da9cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1x3_t*
+fun (vint32m1x3_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1x3_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-9.c b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
new file mode 100644
index 000000000000..b5f130f0caf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
-- 
2.36.3
 

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Jeff Law]

On 6/18/23 07:16, 钟居哲 wrote:
> Thanks for cleaning up codes for future's ABI support patch.
> Let's wait for Jeff or Robin comments.
Looks reasonable to me given the state we're in WRT psabi and vectors.

jeff

RE: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Li, Pan2]

Committed, thanks Jeff.

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Tuesday, June 20, 2023 2:04 AM
To: 钟居哲 <juzhe.zhong@rivai.ai>; 丁乐华 <lehua.ding@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>; palmer <palmer@rivosinc.com>; rdapp.gcc <rdapp.gcc@gmail.com>
Subject: Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code



On 6/18/23 07:16, 钟居哲 wrote:
> Thanks for cleaning up codes for future's ABI support patch.
> Let's wait for Jeff or Robin comments.
Looks reasonable to me given the state we're in WRT psabi and vectors.

jeff

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Robin Dapp]

> Committed, thanks Jeff.

The vec_set/vec_extract tests FAIL since this commit.  I'm going to
commit the attached as obvious.

Lehua, would they not show up in your test runs?  You fixed several
other tests but these somehow not?

Regards
 Robin

Subject: [PATCH] RISC-V: testsuite: Add -Wno-psabi to vec_set/vec_extract
 testcases.

This fixes some fallout from the recent psabi changes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Add
	-Wno-psabi.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Dito.
---
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c    | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c          | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c          | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c          | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c          | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c        | 2 +-
 10 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
index 1a6e6dd83ee..34efd5f700a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
index 884c38e0bd8..5f3168a320a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
index 844ad392df0..7210327a4ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
index 04c234e7d2d..c5cb56a88c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
index dd22dae5eb9..43110c0bb8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
+/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
 
 #include <assert.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
index 4fb4e822b93..28f11150f8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
index 379e92f30bb..1f2aaeaf2df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
index b1e78150b30..dfd1ff2aa86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
index 0b7f53d1cf3..eb63435d2f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
index bf04a3d029e..6a08f26e099 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
+/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
 
 #include <assert.h>
 
-- 
2.40.1

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Lehua Ding]

[-- Attachment #1: Type: text/plain, Size: 381 bytes --]

> Lehua, would they not show up in your test runs?  You fixed several
> other tests but these somehow not?


Oh, I should know why. These cases of yours were added yesterday,
while I submitted the patch the day before, and then yesterday by Pan
to help me merge in after your cases. Sorry for introducing this issue,
I'll submit a new fix patch.


Best,
Lehua

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Robin Dapp]

> Oh, I should know why. These cases of yours were added yesterday,
> while I submitted the patch the day before, and then yesterday by Pan
> to help me merge in after your cases. Sorry for introducing this issue,
> I'll submit a new fix patch.

Actually they are already in for a bit :)
51795b910737 (Robin Dapp 2023-06-01 14:18:57 +0200  1) /* { dg-do compile } */

I thought something is special about them that they somehow didn't run
on your machine or so.

But no need for a new patch, thanks.  I already have it and will commit
it soon.

Regards
 Robin

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Lehua Ding]

[-- Attachment #1: Type: text/plain, Size: 737 bytes --]

> Actually they are already in for a bit :)
> 51795b910737 (Robin Dapp 2023-06-01 14:18:57 +0200  1) /* { dg-do compile } */
>I thought something is special about them that they somehow didn't run
> on your machine or so.


The time I just said is your commit time from this link
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=51795b91073798c718df6fafb01303861641a5af.


authorRobin Dapp&nbsp;<rdapp@ventanamicro.com&gt;
Thu, 1 Jun 2023 12:18:57 +0000&nbsp;(14:18 +0200)
committerRobin Dapp&nbsp;<rdapp@ventanamicro.com&gt;
Mon, 19 Jun 2023 07:58:35 +0000&nbsp;(09:58 +0200)



And I just ran these cases locally and also reported an error.
Are there some good ways to avoid this here?


Best,
Lehua

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Lehua Ding]

[-- Attachment #1: Type: text/plain, Size: 9376 bytes --]

> -/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
> +/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */

By the way, shouldn't these cases have the `-mabi=lp64d` option added,
otherwise I get the following failure message when I run tests on RV32 GCC.


  FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess errors)
  Excess errors.
  cc1: error: ABI requires '-march=rv32'



Best,
Lehua


------------------ Original ------------------
From: &nbsp;"Robin&nbsp;Dapp"<rdapp.gcc@gmail.com&gt;;
Date: &nbsp;Tue, Jun 20, 2023 08:10 PM
To: &nbsp;"pan2.li"<pan2.li@intel.com&gt;; "Jeff Law"<jeffreyalaw@gmail.com&gt;; "钟居哲"<juzhe.zhong@rivai.ai&gt;; "丁乐华"<lehua.ding@rivai.ai&gt;; "gcc-patches"<gcc-patches@gcc.gnu.org&gt;; 
Cc: &nbsp;"Robin Dapp"<rdapp.gcc@gmail.com&gt;; "yanzhang.wang"<yanzhang.wang@intel.com&gt;; "kito.cheng"<kito.cheng@gmail.com&gt;; "palmer"<palmer@rivosinc.com&gt;; 
Subject: &nbsp;Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

&nbsp;

&gt; Committed, thanks Jeff.

The vec_set/vec_extract tests FAIL since this commit.&nbsp; I'm going to
commit the attached as obvious.

Lehua, would they not show up in your test runs?&nbsp; You fixed several
other tests but these somehow not?

Regards
&nbsp;Robin

Subject: [PATCH] RISC-V: testsuite: Add -Wno-psabi to vec_set/vec_extract
&nbsp;testcases.

This fixes some fallout from the recent psabi changes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Add
	-Wno-psabi.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Dito.
---
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 2 +-
&nbsp;10 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
index 1a6e6dd83ee..34efd5f700a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
index 884c38e0bd8..5f3168a320a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
index 844ad392df0..7210327a4ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
index 04c234e7d2d..c5cb56a88c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
index dd22dae5eb9..43110c0bb8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
+/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <assert.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
index 4fb4e822b93..28f11150f8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
index 379e92f30bb..1f2aaeaf2df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
index b1e78150b30..dfd1ff2aa86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
index 0b7f53d1cf3..eb63435d2f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <stdint-gcc.h&gt;
&nbsp;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
index bf04a3d029e..6a08f26e099 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
@@ -1,5 +1,5 @@
&nbsp;/* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
+/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
&nbsp;
&nbsp;#include <assert.h&gt;
&nbsp;
-- 
2.40.1

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Robin Dapp]

> By the way, shouldn't these cases have the `-mabi=lp64d` option added,
> otherwise I get the following failure message when I run tests on RV32 GCC.
> 
>   FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess errors)
>   Excess errors.
>   cc1: error: ABI requires '-march=rv32'

Arg, yes definitely, sorry.  I keep forgetting this... Will fix.

Regards
 Robin

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

[Robin Dapp]

Hi,

I'm going to commit the attached.  Thanks Lehua for reporting.

Regards
 Robin


From 1a4dfe90f251e38e27104f2fa11feecd3b04c4c1 Mon Sep 17 00:00:00 2001
From: Robin Dapp <rdapp@ventanamicro.com>
Date: Tue, 20 Jun 2023 15:52:16 +0200
Subject: [PATCH] RISC-V: testsuite: Add missing -mabi=lp64d.

This fixes more cases of missing -mabi=lp64d.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Add
	-mabi=lp64d.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
---
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c          | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c          | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c          | 2 +-
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c          | 2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index c32c31ecd69..9ed7c4f1205 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
index 34efd5f700a..9cb167a8cdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
index 5f3168a320a..2837ff58e2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
index 7210327a4ff..47f30ed79f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
index c5cb56a88c7..f7169f07506 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
index 28f11150f8f..3d60e635869 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
index 1f2aaeaf2df..6929c17ca4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
index dfd1ff2aa86..903deae7d89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
index eb63435d2f0..7d73399496e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
-- 
2.40.1