Re: [PATCH] RISC-V: Add RVV registers register spilling

[Jeff Law <jeffreyalaw@gmail.com>]

[-- Attachment #1: Type: text/plain, Size: 556 bytes --]


On 11/21/22 02:25, juzhe.zhong@rivai.ai wrote:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606523.html
> This patch obviously didn't include scalable size frame.
> So it ICE in offset = cfun->machine->frame.gp_sp_offset.to_constant ();
> We can't directly use to_constant if the frame is a scalable.
> Please fix it or revert it. Thanks

We probably just need to reject everything in 
riscv_get_setparate_components if the offset isn't constant. Something 
like the attached patch (untested) might be enough to resolve the problem.


Jeff



[-- Attachment #2: P --]
[-- Type: text/plain, Size: 554 bytes --]

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7ec4ce97e6c..7bfc0e9f595 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5340,7 +5340,8 @@ riscv_get_separate_components (void)
   bitmap_clear (components);
 
   if (riscv_use_save_libcall (&cfun->machine->frame)
-      || cfun->machine->interrupt_handler_p)
+      || cfun->machine->interrupt_handler_p
+      || !cfun->machine->frame.gp_sp_offset.is_constant ())
     return components;
 
   offset = cfun->machine->frame.gp_sp_offset.to_constant ();