From: Jeff Law <jeffreyalaw@gmail.com>
To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH] RISC-V: Add testcases for VSETVL PASS
Date: Fri, 16 Dec 2022 13:07:11 -0700 [thread overview]
Message-ID: <1bcbe6fb-74be-34b4-b178-ffb324abca43@gmail.com> (raw)
In-Reply-To: <20221214080931.192028-1-juzhe.zhong@rivai.ai>
On 12/14/22 01:09, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/rvv.exp: Adjust to enable tests for VSETVL PASS.
> * gcc.target/riscv/rvv/vsetvl/dump-1.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: New test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: New test.
So it looks like the assembler strings you're searching for are highly
specific (across all 5 testsuite patches). How sensitive do we expect
these tests to be to things like register allocation giving us different
registers and such? I'd hate to be in a position where we're constantly
needing to update these tests because the output is changing in
unimportant ways.
Jeff
next prev parent reply other threads:[~2022-12-16 20:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-14 8:09 juzhe.zhong
2022-12-16 20:07 ` Jeff Law [this message]
2022-12-17 1:31 ` 钟居哲
2022-12-17 1:42 ` Jeff Law
2022-12-19 3:22 ` Kito Cheng
2022-12-26 9:20 ` Andreas Schwab
2022-12-26 9:28 ` 钟居哲
2022-12-27 15:04 ` Jeff Law
2022-12-27 15:12 ` Kito Cheng
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