From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Christoph Muellner <christoph.muellner@vrull.eu>,
Vineet Gupta <vineetg@rivosinc.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Jeff Law <jlaw@ventanamicro.com>,
Kito Cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH] RISC-V: allow bseti on SImode without sign-extension
Date: Fri, 18 Nov 2022 12:26:26 -0700 [thread overview]
Message-ID: <1c84ef1d-2090-2a93-d391-c8a9b765609d@gmail.com> (raw)
In-Reply-To: <20221108200323.2719563-1-philipp.tomsich@vrull.eu>
On 11/8/22 13:03, Philipp Tomsich wrote:
> As long as the SImode operand is not a partial subreg, we can use a
> bseti without postprocessing to or in a bit, as the middle end is
> smart enough to stay away from the signbit.
>
> gcc/ChangeLog:
>
> * config/riscv/bitmanip.md (*bsetidisi): New pattern.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zbs-bexti-02.c: New test.
OK, with my usual grumble about SUBREGs.
jeff
next prev parent reply other threads:[~2022-11-18 19:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 20:03 Philipp Tomsich
2022-11-18 19:26 ` Jeff Law [this message]
2022-11-18 19:52 ` Philipp Tomsich
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