From: Xi Ruoyao <xry111@xry111.site>
To: Lulu Cheng <chenglulu@loongson.cn>, gcc-patches@gcc.gnu.org
Cc: Chenghua Xu <xuchenghua@loongson.cn>, Wang Xuerui <i@xen0n.name>
Subject: Re: [PATCH v3] loongarch: fix mulsidi3_64bit instruction
Date: Sun, 10 Jul 2022 11:43:18 +0800 [thread overview]
Message-ID: <1e19f9ed89f6d61c36e3ee64c894cdb6d14c1e19.camel@xry111.site> (raw)
In-Reply-To: <c9ac3efa-b131-53ee-d1ad-4c23dbc15198@loongson.cn>
On Sun, 2022-07-10 at 09:45 +0800, Lulu Cheng wrote:
>
> 在 2022/7/9 上午10:56, Xi Ruoyao 写道:
> > v3: Relax scan-assembler pattern in test case mulw_d_w.c. It's
> > because
> > multiplication is Abelian and the compiler may switch the order of
> > operands in the future.
> > -- >8 --
> >
> > (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
> > "mulw.d.w", not "mul.d".
> >
> > gcc/ChangeLog:
> >
> > * config/loongarch/loongarch.md (mulsidi3_64bit): Use
> > mulw.d.w
> > instead of mul.d.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/loongarch/mulw_d_w.c: New test.
> > * gcc.c-torture/execute/mul-sext.c: New test.
> > ---
>
> I think there is no problem with this modification.
>
> Thankes!
>
Pushed r13-1591 and r12-8562.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
prev parent reply other threads:[~2022-07-10 3:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-08 13:18 [PATCH] " Xi Ruoyao
2022-07-08 13:31 ` [PATCH v2] " Xi Ruoyao
2022-07-09 2:56 ` [PATCH v3] " Xi Ruoyao
2022-07-10 1:45 ` Lulu Cheng
2022-07-10 3:43 ` Xi Ruoyao [this message]
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