* [PATCH][AArch64] Fix ICE on (const_double:HF 0.0)
@ 2015-10-26 16:26 Alan Lawrence
2015-11-02 18:04 ` Alan Lawrence
0 siblings, 1 reply; 3+ messages in thread
From: Alan Lawrence @ 2015-10-26 16:26 UTC (permalink / raw)
To: gcc-patches; +Cc: james.greenhalgh, marcus.shawcroft
The included testcase demonstrates the ICE: aarch64_valid_floating_const
(via aarch64_float_const_representable_p) disables HFmode immediates, but
allows 0.0. However, *movhf_aarch64 does not allow this insn:
(insn 7 6 10 2 (set (mem:HF (reg/f:DI 73) [0 *f_2(D)+0 S2 A16])
(const_double:HF 0.0 [0x0.0p+0])) test.c:8 -1
(nil))
Fix is to allow the second operand to be zero, in the same way as
*movsf_aarch64.
Bootstrapped + check-gcc on aarch64-none-linux-gnu.
New test also passing on arm-none-eabi.
OK for trunk?
gcc/ChangeLog:
* config/aarch64/aarch64.md (*movhf_aarch64): Use
aarch64_reg_or_fp_zero for second operand.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/fp16/set_zero_1.c: New.
---
gcc/config/aarch64/aarch64.md | 2 +-
gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 78b9ae2..8895a4e 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1120,7 +1120,7 @@
[(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r")
(match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], HFmode)
- || register_operand (operands[1], HFmode))"
+ || aarch64_reg_or_fp_zero (operands[1], HFmode))"
"@
mov\\t%0.h[0], %w1
umov\\t%w0, %1.h[0]
diff --git a/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
new file mode 100644
index 0000000..36cadfd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* { dg-additional-options "-mfp16-format=ieee" { target "arm*-*-*" } } */
+
+extern void abort (void);
+
+__attribute__ ((noinline))
+void
+setfoo (__fp16 *f)
+{
+ *f = 0.0;
+}
+
+int
+main (int argc, char **argv)
+{
+ __fp16 a = 1.0;
+ setfoo (&a);
+ if (a != 0.0)
+ abort ();
+ return 0;
+}
--
1.9.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][AArch64] Fix ICE on (const_double:HF 0.0)
2015-10-26 16:26 [PATCH][AArch64] Fix ICE on (const_double:HF 0.0) Alan Lawrence
@ 2015-11-02 18:04 ` Alan Lawrence
2015-11-02 18:15 ` James Greenhalgh
0 siblings, 1 reply; 3+ messages in thread
From: Alan Lawrence @ 2015-11-02 18:04 UTC (permalink / raw)
To: gcc-patches; +Cc: james.greenhalgh, marcus.shawcroft
On 26/10/15 16:26, Alan Lawrence wrote:
> The included testcase demonstrates the ICE: aarch64_valid_floating_const
> (via aarch64_float_const_representable_p) disables HFmode immediates, but
> allows 0.0. However, *movhf_aarch64 does not allow this insn:
>
> (insn 7 6 10 2 (set (mem:HF (reg/f:DI 73) [0 *f_2(D)+0 S2 A16])
> (const_double:HF 0.0 [0x0.0p+0])) test.c:8 -1
> (nil))
>
> Fix is to allow the second operand to be zero, in the same way as
> *movsf_aarch64.
>
> Bootstrapped + check-gcc on aarch64-none-linux-gnu.
> New test also passing on arm-none-eabi.
>
> OK for trunk?
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64.md (*movhf_aarch64): Use
> aarch64_reg_or_fp_zero for second operand.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/fp16/set_zero_1.c: New.
> ---
> gcc/config/aarch64/aarch64.md | 2 +-
> gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c | 22 ++++++++++++++++++++++
> 2 files changed, 23 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 78b9ae2..8895a4e 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -1120,7 +1120,7 @@
> [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r")
> (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))]
> "TARGET_FLOAT && (register_operand (operands[0], HFmode)
> - || register_operand (operands[1], HFmode))"
> + || aarch64_reg_or_fp_zero (operands[1], HFmode))"
> "@
> mov\\t%0.h[0], %w1
> umov\\t%w0, %1.h[0]
> diff --git a/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
> new file mode 100644
> index 0000000..36cadfd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
> @@ -0,0 +1,22 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2" } */
> +/* { dg-additional-options "-mfp16-format=ieee" { target "arm*-*-*" } } */
> +
> +extern void abort (void);
> +
> +__attribute__ ((noinline))
> +void
> +setfoo (__fp16 *f)
> +{
> + *f = 0.0;
> +}
> +
> +int
> +main (int argc, char **argv)
> +{
> + __fp16 a = 1.0;
> + setfoo (&a);
> + if (a != 0.0)
> + abort ();
> + return 0;
> +}
>
Ping.
--Alan
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][AArch64] Fix ICE on (const_double:HF 0.0)
2015-11-02 18:04 ` Alan Lawrence
@ 2015-11-02 18:15 ` James Greenhalgh
0 siblings, 0 replies; 3+ messages in thread
From: James Greenhalgh @ 2015-11-02 18:15 UTC (permalink / raw)
To: Alan Lawrence; +Cc: gcc-patches, marcus.shawcroft
On Mon, Nov 02, 2015 at 06:03:58PM +0000, Alan Lawrence wrote:
> On 26/10/15 16:26, Alan Lawrence wrote:
> >The included testcase demonstrates the ICE: aarch64_valid_floating_const
> >(via aarch64_float_const_representable_p) disables HFmode immediates, but
> >allows 0.0. However, *movhf_aarch64 does not allow this insn:
> >
> >(insn 7 6 10 2 (set (mem:HF (reg/f:DI 73) [0 *f_2(D)+0 S2 A16])
> > (const_double:HF 0.0 [0x0.0p+0])) test.c:8 -1
> > (nil))
> >
> >Fix is to allow the second operand to be zero, in the same way as
> >*movsf_aarch64.
> >
> >Bootstrapped + check-gcc on aarch64-none-linux-gnu.
> >New test also passing on arm-none-eabi.
> >
> >OK for trunk?
> >
> >gcc/ChangeLog:
> >
> > * config/aarch64/aarch64.md (*movhf_aarch64): Use
> > aarch64_reg_or_fp_zero for second operand.
> >
> >gcc/testsuite/ChangeLog:
> >
> > * gcc.target/aarch64/fp16/set_zero_1.c: New.
> >---
> > gcc/config/aarch64/aarch64.md | 2 +-
> > gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c | 22 ++++++++++++++++++++++
> > 2 files changed, 23 insertions(+), 1 deletion(-)
> > create mode 100644 gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
> >
> >diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> >index 78b9ae2..8895a4e 100644
> >--- a/gcc/config/aarch64/aarch64.md
> >+++ b/gcc/config/aarch64/aarch64.md
> >@@ -1120,7 +1120,7 @@
> > [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r")
> > (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))]
> > "TARGET_FLOAT && (register_operand (operands[0], HFmode)
> >- || register_operand (operands[1], HFmode))"
> >+ || aarch64_reg_or_fp_zero (operands[1], HFmode))"
> > "@
> > mov\\t%0.h[0], %w1
> > umov\\t%w0, %1.h[0]
> >diff --git a/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
> >new file mode 100644
> >index 0000000..36cadfd
> >--- /dev/null
> >+++ b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c
> >@@ -0,0 +1,22 @@
> >+/* { dg-do run } */
> >+/* { dg-options "-O2" } */
> >+/* { dg-additional-options "-mfp16-format=ieee" { target "arm*-*-*" } } */
> >+
> >+extern void abort (void);
> >+
> >+__attribute__ ((noinline))
> >+void
> >+setfoo (__fp16 *f)
> >+{
> >+ *f = 0.0;
> >+}
> >+
> >+int
> >+main (int argc, char **argv)
> >+{
> >+ __fp16 a = 1.0;
> >+ setfoo (&a);
> >+ if (a != 0.0)
> >+ abort ();
> >+ return 0;
> >+}
> >
>
> Ping.
OK.
Thanks,
James
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-10-26 16:26 [PATCH][AArch64] Fix ICE on (const_double:HF 0.0) Alan Lawrence
2015-11-02 18:04 ` Alan Lawrence
2015-11-02 18:15 ` James Greenhalgh
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