* [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions
@ 2022-03-25 6:20 yulong
2022-03-25 6:20 ` [PATCH 1/3] RISC-V: Add mininal support for Zicbo[mzp] yulong
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: yulong @ 2022-03-25 6:20 UTC (permalink / raw)
To: gcc-patches
Cc: andrew, palmer, kito.cheng, jim.wilson.gcc, wuwei2016, cmuellner,
ptomsich, jiawei, shihua, sinan, yulong-plct
From: yulong-plct <yulong@nj.iscas.ac.cn>
This patchset adds support for three recently ratified RISC-V extensions:
- Zicbom (Cache-Block Management Instructions)
- Zicbop (Cache-Block Prefetch hint instructions)
- Zicboz (Cache-Block Zero Instructions)
The naming of builtin caused oddities, so in this release we have changed the names of builtin. For example, change "__builtin_riscv_zero()" to "__builtin_riscv_zicboz_cbo_zero"
Patch 1: Add Zicbom/z/p mininal support
Patch 2: Add Zicbom/z/p instructions arch support
Patch 3: Add Zicbom/z/p instructions testcases
cf. <https://github.com/riscv/riscv-CMOs/blob/fc8e97a9531ac9811971a182ae431976b86216e1/specifications/cmobase-v1.0-rc2.pdf>;
*** BLURB HERE ***
yulong-plct (3):
RISC-V: Add mininal support for Zicbo[mzp]
RISC-V:Cache Management Operation instructions
RISC-V:Cache Management Operation instructions testcases
gcc/common/config/riscv/riscv-common.cc | 6 +++
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv-builtins.cc | 16 ++++++
gcc/config/riscv/riscv-cmo.def | 17 ++++++
gcc/config/riscv/riscv-ftypes.def | 4 ++
gcc/config/riscv/riscv-opts.h | 9 ++++
gcc/config/riscv/riscv.md | 52 +++++++++++++++++++
gcc/config/riscv/riscv.opt | 3 ++
gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 ++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 ++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 ++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 ++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 ++++
gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 ++++
14 files changed, 217 insertions(+)
create mode 100644 gcc/config/riscv/riscv-cmo.def
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] RISC-V: Add mininal support for Zicbo[mzp]
2022-03-25 6:20 [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions yulong
@ 2022-03-25 6:20 ` yulong
2022-03-25 6:20 ` [PATCH 2/3] RISC-V:Cache Management Operation instructions yulong
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: yulong @ 2022-03-25 6:20 UTC (permalink / raw)
To: gcc-patches
Cc: andrew, palmer, kito.cheng, jim.wilson.gcc, wuwei2016, cmuellner,
ptomsich, jiawei, shihua, sinan, yulong-plct
From: yulong-plct <yulong@nj.iscas.ac.cn>
This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions.
* config/riscv/riscv-opts.h (MASK_ZICBOZ): New.
(MASK_ZICBOM): New.
(MASK_ZICBOP): New.
(TARGET_ZICBOZ): New.
(TARGET_ZICBOM): New.
(TARGET_ZICBOP): New.
* config/riscv/riscv.opt: New.
---
gcc/common/config/riscv/riscv-common.cc | 6 ++++++
gcc/config/riscv/riscv-opts.h | 9 +++++++++
gcc/config/riscv/riscv.opt | 3 +++
3 files changed, 18 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..52c6ac3b1c8 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -164,6 +164,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zksed", ISA_SPEC_CLASS_NONE, 1, 0},
{"zksh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkt", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
{"zk", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkn", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1109,6 +1112,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zksed", &gcc_options::x_riscv_zk_subext, MASK_ZKSED},
{"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
{"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT},
+ {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
+ {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
+ {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
{"zve32x", &gcc_options::x_target_flags, MASK_VECTOR},
{"zve32f", &gcc_options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 15bb5e76854..42a7ff698e7 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,6 +83,15 @@ enum stack_protector_guard {
#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
+#define MASK_ZICBOZ (1 << 0)
+#define MASK_ZICBOM (1 << 1)
+#define MASK_ZICBOP (1 << 2)
+
+
+#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
+#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
+#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
+
#define MASK_ZBKB (1 << 0)
#define MASK_ZBKC (1 << 1)
#define MASK_ZBKX (1 << 2)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 492aad12324..a0722613fcc 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -200,6 +200,9 @@ int riscv_zi_subext
TargetVariable
int riscv_zb_subext
+TargetVariable
+int riscv_zicmo_subext
+
TargetVariable
int riscv_zk_subext
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] RISC-V:Cache Management Operation instructions
2022-03-25 6:20 [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions yulong
2022-03-25 6:20 ` [PATCH 1/3] RISC-V: Add mininal support for Zicbo[mzp] yulong
@ 2022-03-25 6:20 ` yulong
2022-03-25 6:20 ` [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases yulong
2022-04-28 3:27 ` [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions Kito Cheng
3 siblings, 0 replies; 6+ messages in thread
From: yulong @ 2022-03-25 6:20 UTC (permalink / raw)
To: gcc-patches
Cc: andrew, palmer, kito.cheng, jim.wilson.gcc, wuwei2016, cmuellner,
ptomsich, jiawei, shihua, sinan, yulong-plct
From: yulong-plct <yulong@nj.iscas.ac.cn>
This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions.
gcc/ChangeLog:
* config/riscv/predicates.md (imm5_operand): Add a new operand type for prefetch instructions.
* config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA Extensions.
(RISCV_ATYPE_SI): New.
(RISCV_ATYPE_DI): New.
* config/riscv/riscv-ftypes.def (0): New.
(1): New.
* config/riscv/riscv.md (riscv_clean_<mode>): New.
(riscv_flush_<mode>): New.
(riscv_inval_<mode>): New.
(riscv_zero_<mode>): New.
(prefetch): New.
(riscv_prefetchi_<mode>): New.
* config/riscv/riscv-cmo.def: New file.
---
gcc/config/riscv/predicates.md | 4 +++
gcc/config/riscv/riscv-builtins.cc | 16 +++++++++
gcc/config/riscv/riscv-cmo.def | 17 ++++++++++
gcc/config/riscv/riscv-ftypes.def | 4 +++
gcc/config/riscv/riscv.md | 52 ++++++++++++++++++++++++++++++
5 files changed, 93 insertions(+)
create mode 100644 gcc/config/riscv/riscv-cmo.def
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 97cdbdf053b..3fb4d95ab08 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -239,3 +239,7 @@
(define_predicate "const63_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) == 63")))
+
+(define_predicate "imm5_operand"
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) < 5")))
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 0658f8d3047..795132a0c16 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,6 +87,18 @@ struct riscv_builtin_description {
AVAIL (hard_float, TARGET_HARD_FLOAT)
+
+AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT)
+AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT)
+AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
+AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+
/* Construct a riscv_builtin_description from the given arguments.
INSN is the name of the associated instruction pattern, without the
@@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
/* Argument types. */
#define RISCV_ATYPE_VOID void_type_node
#define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_SI intSI_type_node
+#define RISCV_ATYPE_DI intDI_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
@@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
RISCV_ATYPE_##A, RISCV_ATYPE_##B
static const struct riscv_builtin_description riscv_builtins[] = {
+ #include "riscv-cmo.def"
+
DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
};
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
new file mode 100644
index 00000000000..01cbf6ad64f
--- /dev/null
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -0,0 +1,17 @@
+// zicbom
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64),
+
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64),
+
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64),
+
+// zicboz
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64),
+
+// zicbop
+RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32),
+RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64),
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 2214c496f9b..62421292ce7 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,3 +28,7 @@ along with GCC; see the file COPYING3. If not see
DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (1, (VOID, USI))
+DEF_RISCV_FTYPE (0, (SI))
+DEF_RISCV_FTYPE (0, (DI))
+DEF_RISCV_FTYPE (1, (SI, SI))
+DEF_RISCV_FTYPE (1, (DI, DI))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b3c5bce842a..43ad6e5a481 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -45,6 +45,11 @@
;; Stack tie
UNSPEC_TIE
+ UNSPEC_CLEAN
+ UNSPEC_FLUSH
+ UNSPEC_INVAL
+ UNSPEC_ZERO
+ UNSPEC_PREI
])
(define_c_enum "unspecv" [
@@ -69,6 +74,7 @@
;; Stack Smash Protector
UNSPEC_SSP_SET
UNSPEC_SSP_TEST
+
])
(define_constants
@@ -2863,6 +2869,52 @@
"<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
[(set_attr "length" "12")])
+(define_insn "riscv_clean_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_CLEAN)]
+"TARGET_ZICBOM"
+"cbo.clean\t%0"
+)
+
+(define_insn "riscv_flush_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_FLUSH)]
+"TARGET_ZICBOM"
+"cbo.flush\t%0"
+)
+
+(define_insn "riscv_inval_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_INVAL)]
+"TARGET_ZICBOM"
+"cbo.inval\t%0"
+)
+
+(define_insn "riscv_zero_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_ZERO)]
+"TARGET_ZICBOZ"
+"cbo.zero\t%0"
+)
+
+(define_insn "prefetch"
+[(prefetch (match_operand 0 "address_operand" "p")
+ (match_operand 1 "imm5_operand" "i")
+ (match_operand 2 "const_int_operand" "n"))]
+"TARGET_ZICBOP"
+{
+ switch (INTVAL (operands[1]))
+ {
+ case 0: return "prefetch.r\t%a0";
+ case 1: return "prefetch.w\t%a0";
+ default: gcc_unreachable ();
+ }
+})
+
+(define_insn "riscv_prefetchi_<mode>"
+[(unspec:X [(match_operand:X 0 "address_operand" "p")
+ (match_operand:X 1 "imm5_operand" "i")]
+ UNSPEC_PREI)]
+"TARGET_ZICBOP"
+"prefetch.i\t%0"
+)
+
(include "bitmanip.md")
(include "sync.md")
(include "peephole.md")
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases
2022-03-25 6:20 [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions yulong
2022-03-25 6:20 ` [PATCH 1/3] RISC-V: Add mininal support for Zicbo[mzp] yulong
2022-03-25 6:20 ` [PATCH 2/3] RISC-V:Cache Management Operation instructions yulong
@ 2022-03-25 6:20 ` yulong
2022-04-28 3:27 ` [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions Kito Cheng
3 siblings, 0 replies; 6+ messages in thread
From: yulong @ 2022-03-25 6:20 UTC (permalink / raw)
To: gcc-patches
Cc: andrew, palmer, kito.cheng, jim.wilson.gcc, wuwei2016, cmuellner,
ptomsich, jiawei, shihua, sinan, yulong-plct
From: yulong-plct <yulong@nj.iscas.ac.cn>
This commit adds testcases about CMO instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbom-1.c: New test.
* gcc.target/riscv/cmo-zicbom-2.c: New test.
* gcc.target/riscv/cmo-zicbop-1.c: New test.
* gcc.target/riscv/cmo-zicbop-2.c: New test.
* gcc.target/riscv/cmo-zicboz-1.c: New test.
* gcc.target/riscv/cmo-zicboz-2.c: New test.
---
gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 +++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 +++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +++++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +++++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 ++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 ++++++++
6 files changed, 106 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
new file mode 100644
index 00000000000..26f980feb98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+ return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+ return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
new file mode 100644
index 00000000000..a997f22c233
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zicbom -mabi=ilp32" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+ return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+ return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
new file mode 100644
index 00000000000..a6132d4d893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __builtin_prefetch (p, 1, 1);
+ __builtin_prefetch (p, 1, 2);
+ __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+ return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
new file mode 100644
index 00000000000..b88c1e42d99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv32-*-*}}} */
+/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __builtin_prefetch (p, 1, 1);
+ __builtin_prefetch (p, 1, 2);
+ __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+ return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
new file mode 100644
index 00000000000..3f1488a21b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicboz -mabi=lp64" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicboz_cbo_zero();
+}
+
+/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
new file mode 100644
index 00000000000..a707b07a595
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zicboz -mabi=ilp32" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicboz_cbo_zero();
+}
+
+/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
\ No newline at end of file
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions
2022-03-25 6:20 [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions yulong
` (2 preceding siblings ...)
2022-03-25 6:20 ` [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases yulong
@ 2022-04-28 3:27 ` Kito Cheng
3 siblings, 0 replies; 6+ messages in thread
From: Kito Cheng @ 2022-04-28 3:27 UTC (permalink / raw)
To: yulong
Cc: GCC Patches, Christoph Muellner, Philipp Tomsich,
Andrew Waterman, Sinan Lin, jiawei, wuwei2016,
廖仕华
Generally this patch LGTM, but let's defer to GCC 13 :)
For builtin function...I guess we might need a document in
https://github.com/riscv-non-isa/riscv-c-api-doc first.
On Fri, Mar 25, 2022 at 2:21 PM <yulong@nj.iscas.ac.cn> wrote:
>
> From: yulong-plct <yulong@nj.iscas.ac.cn>
>
> This patchset adds support for three recently ratified RISC-V extensions:
>
> - Zicbom (Cache-Block Management Instructions)
> - Zicbop (Cache-Block Prefetch hint instructions)
> - Zicboz (Cache-Block Zero Instructions)
>
> The naming of builtin caused oddities, so in this release we have changed the names of builtin. For example, change "__builtin_riscv_zero()" to "__builtin_riscv_zicboz_cbo_zero"
>
> Patch 1: Add Zicbom/z/p mininal support
> Patch 2: Add Zicbom/z/p instructions arch support
> Patch 3: Add Zicbom/z/p instructions testcases
>
> cf. <https://github.com/riscv/riscv-CMOs/blob/fc8e97a9531ac9811971a182ae431976b86216e1/specifications/cmobase-v1.0-rc2.pdf>;
>
> *** BLURB HERE ***
>
> yulong-plct (3):
> RISC-V: Add mininal support for Zicbo[mzp]
> RISC-V:Cache Management Operation instructions
> RISC-V:Cache Management Operation instructions testcases
>
> gcc/common/config/riscv/riscv-common.cc | 6 +++
> gcc/config/riscv/predicates.md | 4 ++
> gcc/config/riscv/riscv-builtins.cc | 16 ++++++
> gcc/config/riscv/riscv-cmo.def | 17 ++++++
> gcc/config/riscv/riscv-ftypes.def | 4 ++
> gcc/config/riscv/riscv-opts.h | 9 ++++
> gcc/config/riscv/riscv.md | 52 +++++++++++++++++++
> gcc/config/riscv/riscv.opt | 3 ++
> gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 ++++++++
> gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 ++++++++
> gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 ++++++++
> gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 ++++++++
> gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 ++++
> gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 ++++
> 14 files changed, 217 insertions(+)
> create mode 100644 gcc/config/riscv/riscv-cmo.def
> create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] RISC-V:Cache Management Operation instructions
2022-03-04 2:49 yulong
@ 2022-03-04 2:49 ` yulong
0 siblings, 0 replies; 6+ messages in thread
From: yulong @ 2022-03-04 2:49 UTC (permalink / raw)
To: gcc-patches
Cc: andrew, palmer, kito.cheng, jim.wilson.gcc, research_trasio,
wuwei2016, cmuellner, ptomsich, sinan, jiawei, shihua,
yulong-plct
From: yulong-plct <yulong@nj.iscas.ac.cn>
This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions.
7
8 gcc/ChangeLog:
9
10 * config/riscv/predicates.md (imm5_operand): Add a new operand type for prefetch instructions.
11 * config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA Extensions.
12 (RISCV_ATYPE_SI): New.
13 (RISCV_ATYPE_DI): New.
14 * config/riscv/riscv-ftypes.def (0): New.
15 (1): New.
16 * config/riscv/riscv.md (riscv_clean_<mode>): Add a new mode for cbo.clean instruction.
17 (riscv_flush_<mode>): Add a new mode for cbo.flush instruction.
18 (riscv_inval_<mode>): Add a new mode for cbo.inval instruction.
19 (riscv_zero_<mode>): Add a new mode for cbo.zero instruction.
20 (prefetch): Add a new mode for prefetch.r and prefetch.w instructions.
21 (riscv_prefetchi_<mode>): Add a new mode for prefetch.i instruction.
22 * config/riscv/riscv-cmo.def: New file.
---
gcc/config/riscv/predicates.md | 4 +++
gcc/config/riscv/riscv-builtins.cc | 16 +++++++++
gcc/config/riscv/riscv-cmo.def | 17 ++++++++++
gcc/config/riscv/riscv-ftypes.def | 4 +++
gcc/config/riscv/riscv.md | 52 ++++++++++++++++++++++++++++++
5 files changed, 93 insertions(+)
create mode 100644 gcc/config/riscv/riscv-cmo.def
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 97cdbdf053b..3fb4d95ab08 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -239,3 +239,7 @@
(define_predicate "const63_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) == 63")))
+
+(define_predicate "imm5_operand"
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) < 5")))
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 0658f8d3047..795132a0c16 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,6 +87,18 @@ struct riscv_builtin_description {
AVAIL (hard_float, TARGET_HARD_FLOAT)
+
+AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT)
+AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT)
+AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
+AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+
/* Construct a riscv_builtin_description from the given arguments.
INSN is the name of the associated instruction pattern, without the
@@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
/* Argument types. */
#define RISCV_ATYPE_VOID void_type_node
#define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_SI intSI_type_node
+#define RISCV_ATYPE_DI intDI_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
@@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
RISCV_ATYPE_##A, RISCV_ATYPE_##B
static const struct riscv_builtin_description riscv_builtins[] = {
+ #include "riscv-cmo.def"
+
DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
};
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
new file mode 100644
index 00000000000..8829a1d664d
--- /dev/null
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -0,0 +1,17 @@
+// zicbom
+RISCV_BUILTIN (clean_si, "clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32),
+RISCV_BUILTIN (clean_di, "clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64),
+
+RISCV_BUILTIN (flush_si, "flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32),
+RISCV_BUILTIN (flush_di, "flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64),
+
+RISCV_BUILTIN (inval_si, "inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32),
+RISCV_BUILTIN (inval_di, "inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64),
+
+// zicboz
+RISCV_BUILTIN (zero_si, "zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32),
+RISCV_BUILTIN (zero_di, "zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64),
+
+// zicbop
+RISCV_BUILTIN (prefetchi_si, "prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32),
+RISCV_BUILTIN (prefetchi_di, "prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64),
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 2214c496f9b..62421292ce7 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,3 +28,7 @@ along with GCC; see the file COPYING3. If not see
DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (1, (VOID, USI))
+DEF_RISCV_FTYPE (0, (SI))
+DEF_RISCV_FTYPE (0, (DI))
+DEF_RISCV_FTYPE (1, (SI, SI))
+DEF_RISCV_FTYPE (1, (DI, DI))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b3c5bce842a..43ad6e5a481 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -45,6 +45,11 @@
;; Stack tie
UNSPEC_TIE
+ UNSPEC_CLEAN
+ UNSPEC_FLUSH
+ UNSPEC_INVAL
+ UNSPEC_ZERO
+ UNSPEC_PREI
])
(define_c_enum "unspecv" [
@@ -69,6 +74,7 @@
;; Stack Smash Protector
UNSPEC_SSP_SET
UNSPEC_SSP_TEST
+
])
(define_constants
@@ -2863,6 +2869,52 @@
"<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
[(set_attr "length" "12")])
+(define_insn "riscv_clean_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_CLEAN)]
+"TARGET_ZICBOM"
+"cbo.clean\t%0"
+)
+
+(define_insn "riscv_flush_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_FLUSH)]
+"TARGET_ZICBOM"
+"cbo.flush\t%0"
+)
+
+(define_insn "riscv_inval_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_INVAL)]
+"TARGET_ZICBOM"
+"cbo.inval\t%0"
+)
+
+(define_insn "riscv_zero_<mode>"
+[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_ZERO)]
+"TARGET_ZICBOZ"
+"cbo.zero\t%0"
+)
+
+(define_insn "prefetch"
+[(prefetch (match_operand 0 "address_operand" "p")
+ (match_operand 1 "imm5_operand" "i")
+ (match_operand 2 "const_int_operand" "n"))]
+"TARGET_ZICBOP"
+{
+ switch (INTVAL (operands[1]))
+ {
+ case 0: return "prefetch.r\t%a0";
+ case 1: return "prefetch.w\t%a0";
+ default: gcc_unreachable ();
+ }
+})
+
+(define_insn "riscv_prefetchi_<mode>"
+[(unspec:X [(match_operand:X 0 "address_operand" "p")
+ (match_operand:X 1 "imm5_operand" "i")]
+ UNSPEC_PREI)]
+"TARGET_ZICBOP"
+"prefetch.i\t%0"
+)
+
(include "bitmanip.md")
(include "sync.md")
(include "peephole.md")
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-28 3:27 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2022-03-25 6:20 [PATCH 0/3] RISC-V: Add Ratified Cache Management Operation ISA Extensions yulong
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