[RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings

[RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings

[Patrick O'Neill]

This series should not be applied as it causes an ABI break.

This RFC aims to bring the RISCV atomics implementation in line with
the recommended mapping present in table A.6 of the ISA manual.

https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157

This mapping being implemented would result in an ABI break due to
libatomic's LR.aq/SC.rl mapping and the A.6's SEQ_CST store mapping
not enforcing SEQ_CST when placed next to eachother.

This can be seen using the following Herd7 litmus test:

RISCV W-RMW

(*
Seq_cst store along with LR.aq/SC.rl is insufficient for a
seq_cst store, seq_cst RMW mapping.
*)

{
0:x7=A; 0:x8=B;
1:x7=A; 1:x8=B;
}

   P0                  | P1          ;
   ori x1,x0,1         | ori x1,x0,1 ;
   fence rw,w          | fence rw,rw ;
   sw x1,0(x8)         | sw x1,0(x7) ;
   lr.w.aq x3,0(x7)    | fence rw,rw ;
   sc.w.rl x1,x1,0(x7) | lw x2,0(x8) ;

exists (0:x3=0 /\ 1:x2=0)

In GCC for SEQ_CST store, we currently emit fence iorw,ow + amoswap.aq,
which successfully enforces ordering for the given litmus test. This
will only be a problem in GCC if we move the SEQ_CST store to the A.6
mapping.

Note: LLVM implements fence rw,w + sw
https://godbolt.org/z/n68P7ne1W

That means that LLVM isn't compatible with libatomic's LR.aq/SC.rl.

* PR target/89835: The RISC-V target uses amoswap.w for relaxed stores

Patrick O'Neill (7):
  RISCV: Enforce Libatomic LR/SC SEQ_CST
  RISCV: Enforce Atomic Compare Exchange SEQ_CST
  RISCV: Add AMO release bits
  RISCV: Optimize AMO Ops
  RISCV: Optimize LR/SC Pairs
  RISCV: Optimize Atomic Stores
  RISCV: Relax mem_thread_fence

 gcc/config/riscv/riscv-protos.h               |  6 ++
 gcc/config/riscv/riscv.cc                     | 93 +++++++++++++++++--
 gcc/config/riscv/sync.md                      | 46 ++++++---
 .../gcc.target/riscv/amo-thread-fence-1.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-2.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-3.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-4.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-5.c     |  6 ++
 .../gcc.target/riscv/inline-atomics-model-1.c | 12 +++
 .../gcc.target/riscv/inline-atomics-model-2.c | 12 +++
 .../gcc.target/riscv/inline-atomics-model-3.c | 12 +++
 .../gcc.target/riscv/inline-atomics-model-4.c | 12 +++
 .../gcc.target/riscv/inline-atomics-model-5.c | 12 +++
 gcc/testsuite/gcc.target/riscv/pr89835.c      |  9 ++
 libgcc/config/riscv/atomic.c                  |  4 +-
 15 files changed, 223 insertions(+), 25 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c

-- 
2.25.1

[RFC 1/7] RISCV: Enforce Libatomic LR/SC SEQ_CST

[Patrick O'Neill]

Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>

	* atomic.c: Change LR.aq/SC.rl pairs into sequentially
	consistent LR.aqrl/SC.rl pair.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 libgcc/config/riscv/atomic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c
index 7007e7a20e4..834d0d4380e 100644
--- a/libgcc/config/riscv/atomic.c
+++ b/libgcc/config/riscv/atomic.c
@@ -39,7 +39,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     unsigned old, tmp1, tmp2;						\
 									\
     asm volatile ("1:\n\t"						\
-		  "lr.w.aq %[old], %[mem]\n\t"				\
+		  "lr.w.aqrl %[old], %[mem]\n\t"			\
 		  #insn " %[tmp1], %[old], %[value]\n\t"		\
 		  invert						\
 		  "and %[tmp1], %[tmp1], %[mask]\n\t"			\
@@ -73,7 +73,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     unsigned old, tmp1;							\
 									\
     asm volatile ("1:\n\t"						\
-		  "lr.w.aq %[old], %[mem]\n\t"				\
+		  "lr.w.aqrl %[old], %[mem]\n\t"			\
 		  "and %[tmp1], %[old], %[mask]\n\t"			\
 		  "bne %[tmp1], %[o], 1f\n\t"				\
 		  "and %[tmp1], %[old], %[not_mask]\n\t"		\
-- 
2.25.1

[RFC 2/7] RISCV: Enforce Atomic Compare Exchange SEQ_CST

[Patrick O'Neill]

This patch enforces SEQ_CST for atomic compare_exchange ops.

Replace Fence/LR.aq/SC.aq pairs with strong SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>

	* sync.md: Change LR.aq/SC.rl pairs into sequentially
	consistent LR.aqrl/SC.rl pair.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/sync.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 86b41e6b00a..cb4242d7b2f 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -115,8 +115,8 @@
 	 UNSPEC_COMPARE_AND_SWAP))
    (clobber (match_scratch:GPR 6 "=&r"))]
   "TARGET_ATOMIC"
-  "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
-  [(set (attr "length") (const_int 20))])
+  "1:\;lr.<amo>.aqrl\t%0,%1\;bne\t%0,%z2,1f\;sc.<amo>.rl\t%6,%z3,%1\;bnez\t%6,1b\;1:"
+  [(set (attr "length") (const_int 16))])
 
 (define_expand "atomic_compare_and_swap<mode>"
   [(match_operand:SI 0 "register_operand" "")   ;; bool output
-- 
2.25.1

[RFC 3/7] RISCV: Add AMO release bits

[Patrick O'Neill]

This patch sets the relevant .rl bits on amo operations.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>

	* riscv.cc (riscv_print_operand): change behavior of %A to
	include release bits.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aab694..813e771bec7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3652,8 +3652,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       break;
 
     case 'A':
-      if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
+      if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)) &&
+	  riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
+	fputs (".aqrl", file);
+      else if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
 	fputs (".aq", file);
+      else if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
+	fputs (".rl", file);
       break;
 
     case 'F':
-- 
2.25.1

[RFC 4/7] RISCV: Optimize AMO Ops

[Patrick O'Neill]

Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.

This change brings amo ops in line with table A.6 of the ISA manual.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>

	* riscv.cc (riscv_memmodel_needs_amo_acquire): Change function
	name.
	* riscv.cc (riscv_print_operand): Remove unneeded %F case.
	* sync.md: Remove unneeded fences.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 16 +++++-----------
 gcc/config/riscv/sync.md  | 16 ++++++++--------
 2 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 813e771bec7..6da602f1b59 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3589,11 +3589,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
     }
 }
 
-/* Return true if a FENCE should be emitted to before a memory access to
-   implement the release portion of memory model MODEL.  */
+/* Return true if the .RL suffix should be added to an AMO to implement the
+   release portion of memory model MODEL.  */
 
 static bool
-riscv_memmodel_needs_release_fence (enum memmodel model)
+riscv_memmodel_needs_amo_release (enum memmodel model)
 {
   switch (model)
     {
@@ -3622,7 +3622,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
    'R'	Print the low-part relocation associated with OP.
    'C'	Print the integer branch condition for comparison OP.
    'A'	Print the atomic operation suffix for memory model OP.
-   'F'	Print a FENCE if the memory model requires a release.
    'z'	Print x0 if OP is zero, otherwise print OP normally.
    'i'	Print i if the operand is not a register.
    'S'	Print shift-index of single-bit mask OP.
@@ -3653,19 +3652,14 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 
     case 'A':
       if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)) &&
-	  riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
+	  riscv_memmodel_needs_amo_release ((enum memmodel) INTVAL (op)))
 	fputs (".aqrl", file);
       else if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
 	fputs (".aq", file);
-      else if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
+      else if (riscv_memmodel_needs_amo_release ((enum memmodel) INTVAL (op)))
 	fputs (".rl", file);
       break;
 
-    case 'F':
-      if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
-	fputs ("fence iorw,ow; ", file);
-      break;
-
     case 'i':
       if (code != REG)
         fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index cb4242d7b2f..f8a79465ee3 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -65,8 +65,8 @@
        (match_operand:SI 2 "const_int_operand")]      ;; model
       UNSPEC_ATOMIC_STORE))]
   "TARGET_ATOMIC"
-  "%F2amoswap.<amo>%A2 zero,%z1,%0"
-  [(set (attr "length") (const_int 8))])
+  "amoswap.<amo>%A2 zero,%z1,%0"
+  [(set (attr "length") (const_int 4))])
 
 (define_insn "atomic_<atomic_optab><mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+A")
@@ -76,8 +76,8 @@
 	   (match_operand:SI 2 "const_int_operand")] ;; model
 	 UNSPEC_SYNC_OLD_OP))]
   "TARGET_ATOMIC"
-  "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
-  [(set (attr "length") (const_int 8))])
+  "amo<insn>.<amo>%A2 zero,%z1,%0"
+  [(set (attr "length") (const_int 4))])
 
 (define_insn "atomic_fetch_<atomic_optab><mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -89,8 +89,8 @@
 	   (match_operand:SI 3 "const_int_operand")] ;; model
 	 UNSPEC_SYNC_OLD_OP))]
   "TARGET_ATOMIC"
-  "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
-  [(set (attr "length") (const_int 8))])
+  "amo<insn>.<amo>%A3 %0,%z2,%1"
+  [(set (attr "length") (const_int 4))])
 
 (define_insn "atomic_exchange<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -101,8 +101,8 @@
    (set (match_dup 1)
 	(match_operand:GPR 2 "register_operand" "0"))]
   "TARGET_ATOMIC"
-  "%F3amoswap.<amo>%A3 %0,%z2,%1"
-  [(set (attr "length") (const_int 8))])
+  "amoswap.<amo>%A3 %0,%z2,%1"
+  [(set (attr "length") (const_int 4))])
 
 (define_insn "atomic_cas_value_strong<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
-- 
2.25.1

[RFC 5/7] RISCV: Optimize LR/SC Pairs

[Patrick O'Neill]

Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs
as needed.

Atomic compare and exchange ops provide 2 types of memory models. C++17
and later places no restrictions on the relative strength of each model,
so ensure we cover both by using a model that enforces the ordering of
both given models.

This change brings LR/SC ops in line with table A.6 of the ISA manual.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>
	
	* riscv.cc: Add functions to get the parent of two
	memmodels in sync.md.
	* riscv-protos.h: Likewise.
	* sync.md (atomic_cas_value_strong<mode>): Remove static
	.aqrl bits on SC op/.rl bits on LR op and replace with %I, %J
	flags.
	* inline-atomics-model-1.c: New test.
	* inline-atomics-model-2.c: Likewise.
	* inline-atomics-model-3.c: Likewise.
	* inline-atomics-model-4.c: Likewise.
	* inline-atomics-model-5.c: Likewise.
	* inline-atomics-model-6.c: Likewise.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv-protos.h               |  4 ++
 gcc/config/riscv/riscv.cc                     | 68 +++++++++++++++++++
 gcc/config/riscv/sync.md                      | 12 +++-
 .../gcc.target/riscv/inline-atomics-model-1.c | 12 ++++
 .../gcc.target/riscv/inline-atomics-model-2.c | 12 ++++
 .../gcc.target/riscv/inline-atomics-model-3.c | 12 ++++
 .../gcc.target/riscv/inline-atomics-model-4.c | 12 ++++
 .../gcc.target/riscv/inline-atomics-model-5.c | 12 ++++
 8 files changed, 143 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-5.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 20c2381c21a..e32ea86a530 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -22,6 +22,8 @@ along with GCC; see the file COPYING3.  If not see
 #ifndef GCC_RISCV_PROTOS_H
 #define GCC_RISCV_PROTOS_H
 
+#include "memmodel.h"
+
 /* Symbol types we understand.  The order of this list must match that of
    the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST.  */
 enum riscv_symbol_type {
@@ -74,6 +76,8 @@ extern bool riscv_expand_block_move (rtx, rtx, rtx);
 extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
 extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
 extern bool riscv_gpr_save_operation_p (rtx);
+extern enum memmodel riscv_parent_memmodel (enum memmodel, enum memmodel);
+extern enum memmodel riscv_simplify_memmodel (enum memmodel);
 
 /* Routines implemented in riscv-c.cc.  */
 void riscv_cpu_cpp_builtins (cpp_reader *);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6da602f1b59..6fbcd62fe73 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3563,6 +3563,59 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc)
   fputc (')', file);
 }
 
+/* Return the memory model that encapuslates both given models. This assumes
+   SYNC models output equivalent code to non-SYNC models.  */
+
+enum memmodel
+riscv_parent_memmodel (enum memmodel model1, enum memmodel model2)
+{
+  model1 = riscv_simplify_memmodel(model1);
+  model2 = riscv_simplify_memmodel(model2);
+
+  enum memmodel weaker = model1 <= model2 ? model1: model2;
+  enum memmodel stronger = model1 > model2 ? model1: model2;
+
+  switch (stronger)
+    {
+      case MEMMODEL_SEQ_CST:
+      case MEMMODEL_ACQ_REL:
+	return stronger;
+      case MEMMODEL_RELEASE:
+	if (weaker== MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME)
+	  return MEMMODEL_ACQ_REL;
+	else
+	  return stronger;
+      case MEMMODEL_ACQUIRE:
+      case MEMMODEL_CONSUME:
+      case MEMMODEL_RELAXED:
+	return stronger;
+      default:
+	gcc_unreachable ();
+    }
+}
+
+enum memmodel
+riscv_simplify_memmodel(enum memmodel model) {
+  switch (model)
+    {
+      case MEMMODEL_SYNC_SEQ_CST:
+	return MEMMODEL_SEQ_CST;
+      case MEMMODEL_SYNC_ACQUIRE:
+	return MEMMODEL_ACQUIRE;
+      case MEMMODEL_SYNC_RELEASE:
+	return MEMMODEL_RELEASE;
+      case MEMMODEL_SEQ_CST:
+      case MEMMODEL_ACQ_REL:
+      case MEMMODEL_RELEASE:
+      case MEMMODEL_ACQUIRE:
+      case MEMMODEL_CONSUME:
+      case MEMMODEL_RELAXED:
+	return model;
+      default:
+	gcc_unreachable();
+    }
+}
+
 /* Return true if the .AQ suffix should be added to an AMO to implement the
    acquire portion of memory model MODEL.  */
 
@@ -3622,6 +3675,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model)
    'R'	Print the low-part relocation associated with OP.
    'C'	Print the integer branch condition for comparison OP.
    'A'	Print the atomic operation suffix for memory model OP.
+   'I'	Print the LR suffix for memory model OP.
+   'J'	Print the SC suffix for memory model OP.
    'z'	Print x0 if OP is zero, otherwise print OP normally.
    'i'	Print i if the operand is not a register.
    'S'	Print shift-index of single-bit mask OP.
@@ -3660,6 +3715,19 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 	fputs (".rl", file);
       break;
 
+    case 'I':
+      if ((enum memmodel) INTVAL (op) == MEMMODEL_SEQ_CST ||
+	  (enum memmodel) INTVAL (op) == MEMMODEL_SYNC_SEQ_CST)
+	fputs (".aqrl", file);
+      else if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
+	fputs (".aq", file);
+      break;
+
+    case 'J':
+      if (riscv_memmodel_needs_amo_release ((enum memmodel) INTVAL (op)))
+	fputs (".rl", file);
+      break;
+
     case 'i':
       if (code != REG)
         fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index f8a79465ee3..b54338d8eb2 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -115,7 +115,17 @@
 	 UNSPEC_COMPARE_AND_SWAP))
    (clobber (match_scratch:GPR 6 "=&r"))]
   "TARGET_ATOMIC"
-  "1:\;lr.<amo>.aqrl\t%0,%1\;bne\t%0,%z2,1f\;sc.<amo>.rl\t%6,%z3,%1\;bnez\t%6,1b\;1:"
+  {
+    enum memmodel model_success = (enum memmodel) INTVAL(operands[4]);
+    enum memmodel model_failure = (enum memmodel) INTVAL(operands[5]);
+    operands[5] = GEN_INT(riscv_parent_memmodel(model_success, model_failure));
+    return "1:\;"
+	   "lr.<amo>%I5\t%0,%1\;"
+	   "bne\t%0,%z2,1f\;"
+	   "sc.<amo>%J5\t%6,%z3,%1\;"
+	   "bnez\t%6,1b\;"
+	   "1:";
+  }
   [(set (attr "length") (const_int 16))])
 
 (define_expand "atomic_compare_and_swap<mode>"
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-model-1.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-1.c
new file mode 100644
index 00000000000..a2c3fc7a1b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that appropriate bits are placed per memory model.  */
+/* { dg-final { scan-assembler-not "lr.w.aq" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+/* { dg-final { scan-assembler-not "sc.w.rl" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-model-2.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-2.c
new file mode 100644
index 00000000000..d23d4db945f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that appropriate bits are placed per memory model.  */
+/* { dg-final { scan-assembler "lr.w.aq" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+/* { dg-final { scan-assembler-not "sc.w.rl" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-model-3.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-3.c
new file mode 100644
index 00000000000..7379825c6f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that appropriate bits are placed per memory model.  */
+/* { dg-final { scan-assembler "lr.w.aq" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+/* { dg-final { scan-assembler-not "sc.w.rl" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-model-4.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-4.c
new file mode 100644
index 00000000000..80ab9889288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that appropriate bits are placed per memory model.  */
+/* { dg-final { scan-assembler "lr.w.aqrl" } } */
+/* { dg-final { scan-assembler "sc.w.rl" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-model-5.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-5.c
new file mode 100644
index 00000000000..da905242317
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-model-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that appropriate bits are placed per memory model.  */
+/* { dg-final { scan-assembler "lr.w.aq" } } */
+/* { dg-final { scan-assembler "sc.w.rl" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE);
+}
-- 
2.25.1

[RFC 6/7] RISCV: Optimize Atomic Stores

[Patrick O'Neill]

This change brings atomic stores in line with table A.6 of the ISA
manual.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>

	PR target/89835
	* riscv.cc (atomic_cas_value_strong<mode>): Add %I flag for
	atomic store fences.
	* sync.md (atomic_store<mode>): Use simple store instruction in
	combination with a fence.
	* pr89835.c: New test.
	
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv.cc                | 6 ++++++
 gcc/config/riscv/sync.md                 | 2 +-
 gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++
 3 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6fbcd62fe73..48d18a83f06 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3677,6 +3677,7 @@ riscv_memmodel_needs_amo_release (enum memmodel model)
    'A'	Print the atomic operation suffix for memory model OP.
    'I'	Print the LR suffix for memory model OP.
    'J'	Print the SC suffix for memory model OP.
+   'K'  Print a leading fence for the memory model OP.
    'z'	Print x0 if OP is zero, otherwise print OP normally.
    'i'	Print i if the operand is not a register.
    'S'	Print shift-index of single-bit mask OP.
@@ -3728,6 +3729,11 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 	fputs (".rl", file);
       break;
 
+    case 'K':
+      if (riscv_memmodel_needs_amo_release ((enum memmodel) INTVAL (op)))
+	fputs ("fence\trw,w;", file);
+      break;
+
     case 'i':
       if (code != REG)
         fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index b54338d8eb2..1cc3731da38 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -65,7 +65,7 @@
        (match_operand:SI 2 "const_int_operand")]      ;; model
       UNSPEC_ATOMIC_STORE))]
   "TARGET_ATOMIC"
-  "amoswap.<amo>%A2 zero,%z1,%0"
+  "%K2s<amo>\t%z1,%0"
   [(set (attr "length") (const_int 4))])
 
 (define_insn "atomic_<atomic_optab><mode>"
diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c
new file mode 100644
index 00000000000..ab190e11b60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr89835.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* Verify that relaxed atomic stores use simple store instuctions.  */
+/* { dg-final { scan-assembler-not "amoswap" } } */
+
+void
+foo(int bar, int baz)
+{
+  __atomic_store_n(&bar, baz, __ATOMIC_RELAXED);
+}
-- 
2.25.1

[RFC 7/7] RISCV: Relax mem_thread_fence

[Patrick O'Neill]

This change brings atomic fences in line with table A.6 of the ISA
manual.

Relax mem_thread_fence according to the memmodel given.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>

	* riscv.cc: Expose helper functions to sync.md.
	* riscv-protos.h: Likewise.
	* sync.md (mem_thread_fence_1): Change fence depending on
	aquire/release requirements.
	* amo-thread-fence-1: New test.
	* amo-thread-fence-2: Likewise.
	* amo-thread-fence-3: Likewise.
	* amo-thread-fence-4: Likewise.
	* amo-thread-fence-5: Likewise.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv-protos.h                  |  2 ++
 gcc/config/riscv/riscv.cc                        |  4 ++--
 gcc/config/riscv/sync.md                         | 16 +++++++++++++---
 .../gcc.target/riscv/amo-thread-fence-1.c        |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-2.c        |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-3.c        |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-4.c        |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-5.c        |  6 ++++++
 8 files changed, 47 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e32ea86a530..4390ede84f5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -76,6 +76,8 @@ extern bool riscv_expand_block_move (rtx, rtx, rtx);
 extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
 extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
 extern bool riscv_gpr_save_operation_p (rtx);
+extern bool riscv_memmodel_needs_amo_acquire (enum memmodel);
+extern bool riscv_memmodel_needs_amo_release (enum memmodel);
 extern enum memmodel riscv_parent_memmodel (enum memmodel, enum memmodel);
 extern enum memmodel riscv_simplify_memmodel (enum memmodel);
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 48d18a83f06..3ee910261a2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3619,7 +3619,7 @@ riscv_simplify_memmodel(enum memmodel model) {
 /* Return true if the .AQ suffix should be added to an AMO to implement the
    acquire portion of memory model MODEL.  */
 
-static bool
+bool
 riscv_memmodel_needs_amo_acquire (enum memmodel model)
 {
   switch (model)
@@ -3645,7 +3645,7 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
 /* Return true if the .RL suffix should be added to an AMO to implement the
    release portion of memory model MODEL.  */
 
-static bool
+bool
 riscv_memmodel_needs_amo_release (enum memmodel model)
 {
   switch (model)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 1cc3731da38..a7a040180f5 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -46,14 +46,24 @@
   DONE;
 })
 
-;; Until the RISC-V memory model (hence its mapping from C++) is finalized,
-;; conservatively emit a full FENCE.
 (define_insn "mem_thread_fence_1"
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
    (match_operand:SI 1 "const_int_operand" "")] ;; model
   ""
-  "fence\tiorw,iorw")
+  {
+    enum memmodel model = (enum memmodel) INTVAL (operands[1]);
+    if (model == MEMMODEL_ACQ_REL)
+	return "fence.tso";
+    else if (riscv_memmodel_needs_amo_acquire (model) &&
+	     riscv_memmodel_needs_amo_release (model))
+	return "fence\trw,rw";
+    else if (riscv_memmodel_needs_amo_acquire (model))
+	return "fence\tr,rw";
+    else if (riscv_memmodel_needs_amo_release (model))
+	return "fence\trw,w";
+  }
+  [(set (attr "length") (const_int 4))])
 
 ;; Atomic memory operations.
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
new file mode 100644
index 00000000000..833629bf2f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
new file mode 100644
index 00000000000..3395ee41dbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence\tr,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
new file mode 100644
index 00000000000..59cc4e5d394
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence\trw,w" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
new file mode 100644
index 00000000000..2afed9a9e38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence.tso" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c
new file mode 100644
index 00000000000..b8d56c0f066
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence\trw,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_SEQ_CST);
+}
-- 
2.25.1

Re: [RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings

[Patrick O'Neill]

The litmus test in this RFC is flawed since it does not assert that the
LR/SC pair succeeds. The condition in the RFC is permitted iff the LR/SC
pair fails. After correcting this flaw [1][2], the litmus test condition
is correctly forbidden.

This correction does not mean that the A.6 mapping is guaranteed to be
fully compatible with the current GCC/LLVM mapping. This just means that
this particular case does not appear to be an issue.

Thanks,
Patrick

[1] Corrected herd7 litmus test:
RISCV W-RMW

{
0:x7=A; 0:x8=B; 0:x1=1;
1:x7=A; 1:x8=B; 1:x1=1;
}

    P0                  | P1          ;
    fence rw,w          | fence rw,rw ;
    sw x1,0(x8)         | sw x1,0(x7) ;
    lr.w.aq x3,0(x7)    | fence rw,rw ;
    sc.w.rl x2,x1,0(x7) | lw x2,0(x8) ;

~exists (0:x2=0 /\ 0:x3=0 /\ 1:x2=0)

[2] Corrected herd7 litmus test (with retry-loop):
RISCV W-RMW

{
0:x7=A; 0:x8=B; 0:x1=1;
1:x7=A; 1:x8=B; 1:x1=1;
}

    P0                  | P1          ;
    fence rw,w          | sw x1,0(x7) ;
    sw x1,0(x8)         | fence rw,rw ;
    LC00:               | lw x2,0(x8) ;
    lr.w.aq x3,0(x7)    |             ;
    sc.w.rl x2,x1,0(x7) |             ;
    bne x2,x0,LC00      |             ;

~exists (0:x2=0 /\ 0:x3=0 /\ 1:x2=0)