* [PATCH v3 0/3] RISC-V: Support z[f/d]inx extension
@ 2022-05-23 10:04 jiawei
2022-05-23 10:04 ` [PATCH v3 1/3] RISC-V: Minimal support of " jiawei
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: jiawei @ 2022-05-23 10:04 UTC (permalink / raw)
To: gcc-patches
Cc: palmer, jim.wilson.gcc, kito.cheng, jeremy.bennett,
tariqandlaura, wuwei2016, Jia-Wei Chen
From: Jia-Wei Chen <jiawei@iscas.ac.cn>
Zfinx extension[1] had already finished public review. Here is the
implementation patch set that reuse floating point pattern and ban
the use of fpr when use zfinx as a target.
Current works can be find in follow links, will keep update zhinx
and zhinxmin soon after zfh/zfhmin implemented in gcc.
https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
https://github.com/pz9115/riscv-binutils-gdb/tree/zfinx-rebase
For test you can use qemu or spike that support zfinx extension, the
qemu will go upstream soon and spike is still in review:
https://github.com/plctlab/plct-qemu/tree/plct-zfinx-dev
https://github.com/plctlab/plct-spike/tree/plct-upstream-zfinx
Thanks for Tariq Kurd, Kito Cheng, Jim Willson,
Jeremy Bennett helped us a lot with this work.
[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf
Version log:
v2: As Kito Cheng's comment, add Changelog part in patches, update imply
info in riscv-common.c, remove useless check and update annotation in
riscv.c.
v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.
jiawei (3):
RISC-V: Minimal support of zfinx extension.
RISC-V: Target support for zfinx extension.
RISC-V: Limit regs use for zfinx extension.
gcc/common/config/riscv/riscv-common.cc | 9 ++++
gcc/config/riscv/arch-canonicalize | 3 ++
gcc/config/riscv/constraints.md | 4 +-
gcc/config/riscv/riscv-builtins.cc | 4 +-
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 14 ++++-
gcc/config/riscv/riscv.md | 72 ++++++++++++-------------
gcc/config/riscv/riscv.opt | 3 ++
9 files changed, 75 insertions(+), 42 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v3 1/3] RISC-V: Minimal support of z[f/d]inx extension.
2022-05-23 10:04 [PATCH v3 0/3] RISC-V: Support z[f/d]inx extension jiawei
@ 2022-05-23 10:04 ` jiawei
2022-05-23 10:04 ` [PATCH v3 2/3] RISC-V: Target support for " jiawei
2022-05-23 10:04 ` [PATCH v3 3/3] RISC-V: Limit regs use " jiawei
2 siblings, 0 replies; 4+ messages in thread
From: jiawei @ 2022-05-23 10:04 UTC (permalink / raw)
To: gcc-patches
Cc: palmer, jim.wilson.gcc, kito.cheng, jeremy.bennett,
tariqandlaura, wuwei2016, Jia-Wei Chen
From: Jia-Wei Chen <jiawei@iscas.ac.cn>
Minimal support of zfinx extension, include 'zfinx' and 'zdinx'
corresponding to 'f' and 'd', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f'.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add z[f/d]inx extension info.
* config/riscv/arch-canonicalize: Add imply info.
* config/riscv/riscv-opts.h (MASK_ZFINX): New.
(MASK_ZDINX): Ditto.
(TARGET_ZFINX): Ditto.
(TARGET_ZDINX): Ditto.
* config/riscv/riscv.opt: New.
Co-Authored-By: Sinan Lin
---
gcc/common/config/riscv/riscv-common.cc | 9 +++++++++
gcc/config/riscv/arch-canonicalize | 3 +++
gcc/config/riscv/riscv-opts.h | 6 ++++++
gcc/config/riscv/riscv.opt | 3 +++
4 files changed, 21 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..124bccb23ce 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -50,6 +50,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"d", "f"},
{"f", "zicsr"},
{"d", "zicsr"},
+ {"zdinx", "zfinx"},
+ {"zfinx", "zicsr"},
+
{"zk", "zkn"},
{"zk", "zkr"},
{"zk", "zkt"},
@@ -154,6 +157,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zbkb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbkc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbkx", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1099,6 +1105,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
{"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS},
+ {"zfinx", &gcc_options::x_riscv_zf_subext, MASK_ZFINX},
+ {"zdinx", &gcc_options::x_riscv_zf_subext, MASK_ZDINX},
+
{"zbkb", &gcc_options::x_riscv_zk_subext, MASK_ZBKB},
{"zbkc", &gcc_options::x_riscv_zk_subext, MASK_ZBKC},
{"zbkx", &gcc_options::x_riscv_zk_subext, MASK_ZBKX},
diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index 41bab69193c..e4cfae40b8a 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -41,6 +41,9 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
IMPLIED_EXT = {
"d" : ["f", "zicsr"],
"f" : ["zicsr"],
+ "zdinx" : ["zfinx", "zicsr"],
+ "zfinx" : ["zicsr"],
+
"zk" : ["zkn", "zkr", "zkt"],
"zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"],
"zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"],
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 15bb5e76854..4faf62616d3 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,6 +83,12 @@ enum stack_protector_guard {
#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
+#define MASK_ZFINX (1 << 0)
+#define MASK_ZDINX (1 << 0)
+
+#define TARGET_ZFINX ((riscv_zf_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX ((riscv_zf_subext & MASK_ZDINX) != 0)
+
#define MASK_ZBKB (1 << 0)
#define MASK_ZBKC (1 << 1)
#define MASK_ZBKX (1 << 2)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 84c8cf5a2de..18fd11e3a51 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -200,6 +200,9 @@ int riscv_zi_subext
TargetVariable
int riscv_zb_subext
+TargetVariable
+int riscv_zf_subext
+
TargetVariable
int riscv_zk_subext
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v3 2/3] RISC-V: Target support for z[f/d]inx extension.
2022-05-23 10:04 [PATCH v3 0/3] RISC-V: Support z[f/d]inx extension jiawei
2022-05-23 10:04 ` [PATCH v3 1/3] RISC-V: Minimal support of " jiawei
@ 2022-05-23 10:04 ` jiawei
2022-05-23 10:04 ` [PATCH v3 3/3] RISC-V: Limit regs use " jiawei
2 siblings, 0 replies; 4+ messages in thread
From: jiawei @ 2022-05-23 10:04 UTC (permalink / raw)
To: gcc-patches
Cc: palmer, jim.wilson.gcc, kito.cheng, jeremy.bennett,
tariqandlaura, wuwei2016, Jia-Wei Chen
From: Jia-Wei Chen <jiawei@iscas.ac.cn>
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT' and 'TARGET_DOUBLE_FLOAT' patterns.
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (AVAIL): Add TARGET_ZFINX.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add TARGET_ZFINX.
* config/riscv/riscv.md (TARGET_HARD_FLOAT): Add TARGET_ZFINX.
(TARGET_HARD_FLOAT || TARGET_ZFINX): Add TARGET_ZFINX.
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX): Add TARGET_ZDINX.
Co-Authored-By: Sinan Lin.
---
gcc/config/riscv/riscv-builtins.cc | 4 +-
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv.md | 76 +++++++++++++++---------------
3 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 0658f8d3047..21896d747f5 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -85,7 +85,7 @@ struct riscv_builtin_description {
unsigned int (*avail) (void);
};
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
/* Construct a riscv_builtin_description from the given arguments.
@@ -279,7 +279,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
void
riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
- if (!TARGET_HARD_FLOAT)
+ if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
return;
tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index eb7ef09297e..a9c43a64fd4 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -58,7 +58,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
if (TARGET_HARD_FLOAT)
builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
- if (TARGET_HARD_FLOAT && TARGET_FDIV)
+ if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
{
builtin_define ("__riscv_fdiv");
builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d9b451be0b4..f81e315666e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -300,8 +300,8 @@
(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
- (DF "TARGET_DOUBLE_FLOAT")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+ (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")])
;; Iterator for floating-point modes that can be loaded into X registers.
(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")])
@@ -448,7 +448,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fadd.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -579,7 +579,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -749,7 +749,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmul.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "<UNITMODE>")])
@@ -1056,7 +1056,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT && TARGET_FDIV"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
"fdiv.<fmt>\t%0,%1,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "<UNITMODE>")])
@@ -1071,7 +1071,7 @@
(define_insn "sqrt<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT && TARGET_FDIV"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
{
return "fsqrt.<fmt>\t%0,%1";
}
@@ -1086,7 +1086,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1097,7 +1097,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1109,7 +1109,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fnmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1121,7 +1121,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fnmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1134,7 +1134,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1147,7 +1147,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1160,7 +1160,7 @@
(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1173,7 +1173,7 @@
(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1188,7 +1188,7 @@
(define_insn "abs<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fabs.<fmt>\t%0,%1"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1198,7 +1198,7 @@
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")]
UNSPEC_COPYSIGN))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsgnj.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1206,7 +1206,7 @@
(define_insn "neg<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fneg.<fmt>\t%0,%1"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1223,7 +1223,7 @@
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f"))
(use (match_operand:ANYF 2 "register_operand" " f"))]
UNSPEC_FMIN))]
- "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1233,7 +1233,7 @@
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f"))
(use (match_operand:ANYF 2 "register_operand" " f"))]
UNSPEC_FMAX))]
- "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1242,7 +1242,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smin:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1251,7 +1251,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smax:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1312,7 +1312,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float_truncate:SF
(match_operand:DF 1 "register_operand" " f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
"fcvt.s.d\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
@@ -1438,7 +1438,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF
(match_operand:SF 1 "register_operand" " f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
"fcvt.d.s\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")])
@@ -1454,7 +1454,7 @@
[(set (match_operand:GPR 0 "register_operand" "=r")
(fix:GPR
(match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,rtz"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1463,7 +1463,7 @@
[(set (match_operand:GPR 0 "register_operand" "=r")
(unsigned_fix:GPR
(match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>u.<ANYF:fmt> %0,%1,rtz"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1472,7 +1472,7 @@
[(set (match_operand:ANYF 0 "register_operand" "= f")
(float:ANYF
(match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<ANYF:fmt>.<GPR:ifmt>\t%0,%z1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1481,7 +1481,7 @@
[(set (match_operand:ANYF 0 "register_operand" "= f")
(unsigned_float:ANYF
(match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<ANYF:fmt>.<GPR:ifmt>u\t%0,%z1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1491,7 +1491,7 @@
(unspec:GPR
[(match_operand:ANYF 1 "register_operand" " f")]
RINT))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1765,7 +1765,7 @@
(define_insn "*movdf_hardfloat_rv32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m, *r,*r,*m")
(match_operand:DF 1 "move_operand" " f,G,m,f,G,*r*G,*m,*r"))]
- "!TARGET_64BIT && TARGET_DOUBLE_FLOAT
+ "!TARGET_64BIT && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
@@ -2214,7 +2214,7 @@
(match_operand:ANYF 2 "register_operand")])
(label_ref (match_operand 3 ""))
(pc)))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
operands[1], operands[2]);
@@ -2303,7 +2303,7 @@
(match_operator:SI 1 "fp_scc_comparison"
[(match_operand:ANYF 2 "register_operand")
(match_operand:ANYF 3 "register_operand")]))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2],
operands[3]);
@@ -2315,7 +2315,7 @@
(match_operator:X 1 "fp_native_comparison"
[(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")]))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"f%C1.<fmt>\t%0,%2,%3"
[(set_attr "type" "fcmp")
(set_attr "mode" "<UNITMODE>")])
@@ -2327,7 +2327,7 @@
(match_operand:ANYF 2 "register_operand")]
QUIET_COMPARISON))
(clobber (match_scratch:X 3))])]
- "TARGET_HARD_FLOAT")
+ "TARGET_HARD_FLOAT || TARGET_ZFINX")
(define_insn "*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default"
[(set (match_operand:X 0 "register_operand" "=r")
@@ -2336,7 +2336,7 @@
(match_operand:ANYF 2 "register_operand" " f")]
QUIET_COMPARISON))
(clobber (match_scratch:X 3 "=&r"))]
- "TARGET_HARD_FLOAT && ! HONOR_SNANS (<ANYF:MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ! HONOR_SNANS (<ANYF:MODE>mode)"
"frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3"
[(set_attr "type" "fcmp")
(set_attr "mode" "<UNITMODE>")
@@ -2349,7 +2349,7 @@
(match_operand:ANYF 2 "register_operand" " f")]
QUIET_COMPARISON))
(clobber (match_scratch:X 3 "=&r"))]
- "TARGET_HARD_FLOAT && HONOR_SNANS (<ANYF:MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && HONOR_SNANS (<ANYF:MODE>mode)"
"frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3\n\tfeq.<fmt>\tzero,%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "<UNITMODE>")
@@ -2753,12 +2753,12 @@
(define_insn "riscv_frflags"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"frflags\t%0")
(define_insn "riscv_fsflags"
[(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsflags\t%0")
(define_insn "riscv_mret"
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v3 3/3] RISC-V: Limit regs use for z[f/d]inx extension.
2022-05-23 10:04 [PATCH v3 0/3] RISC-V: Support z[f/d]inx extension jiawei
2022-05-23 10:04 ` [PATCH v3 1/3] RISC-V: Minimal support of " jiawei
2022-05-23 10:04 ` [PATCH v3 2/3] RISC-V: Target support for " jiawei
@ 2022-05-23 10:04 ` jiawei
2 siblings, 0 replies; 4+ messages in thread
From: jiawei @ 2022-05-23 10:04 UTC (permalink / raw)
To: gcc-patches
Cc: palmer, jim.wilson.gcc, kito.cheng, jeremy.bennett,
tariqandlaura, wuwei2016, Jia-Wei Chen
From: Jia-Wei Chen <jiawei@iscas.ac.cn>
Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 'zdinx' enable.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_HARD_FLOAT ? FP_REGS :
((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)):
Use gpr when zfinx or zdinx enable.
* config/riscv/riscv.c (riscv_hard_regno_mode_ok): Add TARGET_ZFINX.
(riscv_option_override): Ditto.
(riscv_abi): Add ABI limit for zfinx with ilp32/lp64.
Co-Authored-By: Sinan Lin.
---
gcc/config/riscv/constraints.md | 4 ++--
gcc/config/riscv/riscv.cc | 14 +++++++++++++-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index bafa4188ccb..0b3d55fee19 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -21,8 +21,8 @@
;; Register constraints
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
- "A floating-point register (if available).")
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)"
+ "A floating-point register (if available, reuse GPR as FPR when use zfinx).")
(define_register_constraint "j" "SIBCALL_REGS"
"@internal")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aab694..01deef54480 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4789,6 +4789,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
!= call_used_or_fixed_reg_p (regno + i))
return false;
+ /* Only use even registers in RV32 ZDINX */
+ if (!TARGET_64BIT && TARGET_ZDINX){
+ if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+ GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+ return !(regno & 1);
+ }
+
return true;
}
@@ -4980,7 +4987,7 @@ riscv_option_override (void)
error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
/* Likewise floating-point division and square root. */
- if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+ if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
target_flags |= MASK_FDIV;
/* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5026,6 +5033,11 @@ riscv_option_override (void)
if (TARGET_RVE && riscv_abi != ABI_ILP32E)
error ("rv32e requires ilp32e ABI");
+ // Zfinx require abi ilp32,ilp32e or lp64.
+ if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+ && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+ error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-05-23 10:04 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-05-23 10:04 [PATCH v3 0/3] RISC-V: Support z[f/d]inx extension jiawei
2022-05-23 10:04 ` [PATCH v3 1/3] RISC-V: Minimal support of " jiawei
2022-05-23 10:04 ` [PATCH v3 2/3] RISC-V: Target support for " jiawei
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