From: Segher Boessenkool <segher@kernel.crashing.org>
To: Peter Bergner <bergner@linux.ibm.com>
Cc: Jiufu Guo <guojiufu@linux.ibm.com>,
meissner@linux.ibm.com, gcc-patches@gcc.gnu.org,
linkw@gcc.gnu.org, dje.gcc@gmail.com
Subject: Re: [PATCH 1/2] Using pli(paddi) and rotate to build 64bit constants
Date: Fri, 2 Sep 2022 11:20:30 -0500 [thread overview]
Message-ID: <20220902162030.GR25951@gate.crashing.org> (raw)
In-Reply-To: <cc37e00f-7849-93f3-09be-f50711439f63@linux.ibm.com>
On Fri, Sep 02, 2022 at 10:29:35AM -0500, Peter Bergner wrote:
> On 9/1/22 4:52 PM, Segher Boessenkool wrote:
> > On Thu, Sep 01, 2022 at 11:24:00AM +0800, Jiufu Guo wrote:
> >> As mentioned in PR106550, since pli could support 34bits immediate, we could
> >> use less instructions(3insn would be ok) to build 64bits constant with pli.
> >
> >> For example, for constant 0x020805006106003, we could generate it with:
> >> asm code1:
> >> pli 9,101736451 (0x6106003)
> >> sldi 9,9,32
> >> paddi 9,9, 2130000 (0x0208050)
> >
> > 3 insns, 2 insns dependent on the previous, each.
> >
> >> or asm code2:
> >> pli 10, 2130000
> >> pli 9, 101736451
> >> rldimi 9, 10, 32, 0
> >
> > 3 insns, 1 insn dependent on both others.
>
> Yeah, the improvement here is the fewer dependent instructions, since
> 2 64-bit + 1 32-bit instructions is the same size as 5 32-bit insns.
It also helps CSE if you do say 0x1200aa00bb0034 and 0x1200aa00bb0056,
or even just 0x1200aa001200aa maybe (we probably have a separate pattern
for the latter though :-) )
Segher
next prev parent reply other threads:[~2022-09-02 16:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 3:24 Jiufu Guo
2022-09-01 21:52 ` Segher Boessenkool
2022-09-02 6:56 ` Jiufu Guo
2022-09-02 16:12 ` Segher Boessenkool
2022-09-05 6:25 ` Jiufu Guo
2022-09-05 13:42 ` Segher Boessenkool
2022-09-06 12:34 ` Jiufu Guo
2022-09-02 15:29 ` Peter Bergner
2022-09-02 16:20 ` Segher Boessenkool [this message]
2022-09-02 4:07 ` Kewen.Lin
2022-09-05 6:22 ` Jiufu Guo
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