[PATCH] Fix _mm512_cvt_roundps_ph to generate sae instruction.

[liuhongt <hongtao.liu@intel.com>]

zmm-version vcvtps2ph is special, it encodes {sae} in evex, but put
round control in the imm. For intrinsic _mm512_cvt_roundps_ph (a,
imm), imm contains both {sae} and round control, we need to separate
it in the assembly output since vcvtps2ph will ignore imm[3:7].

Corresponding llvm patch.
Intrinsic guide will also be updated in the next version.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
Ready to install.

gcc/ChangeLog:

	* config/i386/i386-builtin.def (IX86_BUILTIN_CVTPS2PH512):
	Map to CODE_FOR_avx512f_vcvtps2ph512_mask_sae.
	* config/i386/sse.md (<mask_codefor>avx512f_vcvtps2ph512<mask_name>): Extend to ..
	(<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>): .. this.
	(avx512f_vcvtps2ph512_mask_sae): New expander

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512f-vcvtps2ph-sae.c: New test.
---
 gcc/config/i386/i386-builtin.def              |  2 +-
 gcc/config/i386/sse.md                        | 30 +++++++++++++++++--
 .../gcc.target/i386/avx512f-vcvtps2ph-sae.c   | 18 +++++++++++
 3 files changed, 47 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c

diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index f9c7abde2cf..dea52a28d28 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -1351,7 +1351,7 @@ BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia
 BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI)
 BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI)
 BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI)
-BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask,  "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI)
+BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask_sae,  "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI)
 BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI)
 BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT)
 BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 259048481b6..a35b0d368e6 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -26902,14 +26902,40 @@ (define_insn "*vcvtps2ph256<merge_mask_name>"
    (set_attr "btver2_decode" "vector")
    (set_attr "mode" "V8SF")])
 
-(define_insn "<mask_codefor>avx512f_vcvtps2ph512<mask_name>"
+;; vcvtps2ph is special, it encodes {sae} in evex, but round control in the imm
+;; For intrinsic _mm512_cvt_roundps_ph (a, imm), imm contains both {sae}
+;; and round control, we need to separate it in the assembly output.
+;; op2 in avx512f_vcvtps2ph512_mask_sae contains both sae and round control.
+(define_expand "avx512f_vcvtps2ph512_mask_sae"
+ [(set (match_operand:V16HI 0 "register_operand" "=v")
+       (vec_merge:V16HI
+	 (unspec:V16HI
+	   [(match_operand:V16SF 1 "register_operand" "v")
+	   (match_operand:SI 2 "const_0_to_255_operand")]
+	   UNSPEC_VCVTPS2PH)
+	 (match_operand:V16HI 3 "nonimm_or_0_operand")
+	 (match_operand:HI 4 "register_operand")))]
+  "TARGET_AVX512F"
+{
+  int round = INTVAL (operands[2]);
+  /* Separate {sae} from rounding control imm,
+     imm[3:7] will be ignored by the instruction.  */
+  if (round & 8)
+    {
+      emit_insn (gen_avx512f_vcvtps2ph512_mask_round (operands[0], operands[1],
+	  operands[2], operands[3], operands[4], GEN_INT (8)));
+      DONE;
+    }
+})
+
+(define_insn "<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>"
   [(set (match_operand:V16HI 0 "register_operand" "=v")
 	(unspec:V16HI
 	  [(match_operand:V16SF 1 "register_operand" "v")
 	   (match_operand:SI 2 "const_0_to_255_operand")]
 	  UNSPEC_VCVTPS2PH))]
   "TARGET_AVX512F"
-  "vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  "vcvtps2ph\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "evex")
    (set_attr "mode" "V16SF")])
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c
new file mode 100644
index 00000000000..e0714d437d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)"  1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m256i y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_cvtps_ph (x, 8);
+  y = _mm512_maskz_cvtps_ph (4, x, 9);
+  y = _mm512_mask_cvtps_ph (y, 2, x, 10);
+}
-- 
2.27.0