From: jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@rivosinc.com,
christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn,
Jiawei <jiawei@iscas.ac.cn>
Subject: [v4 PATCH 2/4] RISC-V: Target support for z*inx extension.
Date: Thu, 20 Oct 2022 17:32:33 +0800 [thread overview]
Message-ID: <20221020093235.5071-3-jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20221020093235.5071-1-jiawei@iscas.ac.cn>
From: Jiawei <jiawei@iscas.ac.cn>
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT', 'TARGET_DOUBLE_FLOAT' and 'TARGET_ZHINX' patterns.
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_ZFINX):New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
* config/riscv/riscv-builtins.cc (AVAIL): Ditto.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Ditto.
* config/riscv/riscv.md: Ditto.
---
gcc/config/riscv/iterators.md | 6 +--
gcc/config/riscv/riscv-builtins.cc | 4 +-
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv.md | 78 +++++++++++++++---------------
4 files changed, 46 insertions(+), 44 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 39dffabc235..50380ecfac9 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -59,9 +59,9 @@
(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
- (DF "TARGET_DOUBLE_FLOAT")
- (HF "TARGET_ZFH")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+ (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
+ (HF "TARGET_ZFH || TARGET_ZHINX")])
;; Iterator for floating-point modes that can be loaded into X registers.
(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 14865d70955..1534cfd860b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,7 +87,7 @@ struct riscv_builtin_description {
unsigned int (*avail) (void);
};
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
@@ -322,7 +322,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
void
riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
- if (!TARGET_HARD_FLOAT)
+ if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
return;
tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 78f6eacb068..826ae0067bb 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -61,7 +61,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
if (TARGET_HARD_FLOAT)
builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
- if (TARGET_HARD_FLOAT && TARGET_FDIV)
+ if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
{
builtin_define ("__riscv_fdiv");
builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2d1cda2b98f..09ca91fb2c3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -434,7 +434,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fadd.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -565,7 +565,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -735,7 +735,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmul.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "<UNITMODE>")])
@@ -1042,7 +1042,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT && TARGET_FDIV"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
"fdiv.<fmt>\t%0,%1,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "<UNITMODE>")])
@@ -1057,7 +1057,7 @@
(define_insn "sqrt<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT && TARGET_FDIV"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
{
return "fsqrt.<fmt>\t%0,%1";
}
@@ -1072,7 +1072,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1083,7 +1083,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1095,7 +1095,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fnmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1107,7 +1107,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fnmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1120,7 +1120,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1133,7 +1133,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1146,7 +1146,7 @@
(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1159,7 +1159,7 @@
(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1174,7 +1174,7 @@
(define_insn "abs<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fabs.<fmt>\t%0,%1"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1184,7 +1184,7 @@
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")]
UNSPEC_COPYSIGN))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsgnj.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1192,7 +1192,7 @@
(define_insn "neg<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fneg.<fmt>\t%0,%1"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1209,7 +1209,7 @@
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f"))
(use (match_operand:ANYF 2 "register_operand" " f"))]
UNSPEC_FMIN))]
- "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1219,7 +1219,7 @@
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f"))
(use (match_operand:ANYF 2 "register_operand" " f"))]
UNSPEC_FMAX))]
- "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1228,7 +1228,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smin:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1237,7 +1237,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smax:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1298,7 +1298,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float_truncate:SF
(match_operand:DF 1 "register_operand" " f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
"fcvt.s.d\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
@@ -1307,7 +1307,7 @@
[(set (match_operand:HF 0 "register_operand" "=f")
(float_truncate:HF
(match_operand:SF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN"
+ "TARGET_ZFHMIN || TARGET_ZHINXMIN"
"fcvt.h.s\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "HF")])
@@ -1316,7 +1316,8 @@
[(set (match_operand:HF 0 "register_operand" "=f")
(float_truncate:HF
(match_operand:DF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT"
+ "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
+ (TARGET_ZHINXMIN && TARGET_ZDINX)"
"fcvt.h.d\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "HF")])
@@ -1442,7 +1443,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float_extend:SF
(match_operand:HF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN"
+ "TARGET_ZFHMIN || TARGET_ZHINXMIN"
"fcvt.s.h\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
@@ -1451,7 +1452,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF
(match_operand:SF 1 "register_operand" " f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
"fcvt.d.s\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")])
@@ -1460,7 +1461,8 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF
(match_operand:HF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT"
+ "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
+ (TARGET_ZHINXMIN && TARGET_ZDINX)"
"fcvt.d.h\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")])
@@ -1506,7 +1508,7 @@
[(set (match_operand:GPR 0 "register_operand" "=r")
(fix:GPR
(match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,rtz"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1515,7 +1517,7 @@
[(set (match_operand:GPR 0 "register_operand" "=r")
(unsigned_fix:GPR
(match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>u.<ANYF:fmt> %0,%1,rtz"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1524,7 +1526,7 @@
[(set (match_operand:ANYF 0 "register_operand" "= f")
(float:ANYF
(match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<ANYF:fmt>.<GPR:ifmt>\t%0,%z1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1533,7 +1535,7 @@
[(set (match_operand:ANYF 0 "register_operand" "= f")
(unsigned_float:ANYF
(match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<ANYF:fmt>.<GPR:ifmt>u\t%0,%z1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1543,7 +1545,7 @@
(unspec:GPR
[(match_operand:ANYF 1 "register_operand" " f")]
RINT))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -2271,7 +2273,7 @@
(match_operand:ANYF 2 "register_operand")])
(label_ref (match_operand 3 ""))
(pc)))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
operands[1], operands[2]);
@@ -2360,7 +2362,7 @@
(match_operator:SI 1 "fp_scc_comparison"
[(match_operand:ANYF 2 "register_operand")
(match_operand:ANYF 3 "register_operand")]))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2],
operands[3]);
@@ -2372,7 +2374,7 @@
(match_operator:X 1 "fp_native_comparison"
[(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")]))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"f%C1.<fmt>\t%0,%2,%3"
[(set_attr "type" "fcmp")
(set_attr "mode" "<UNITMODE>")])
@@ -2382,7 +2384,7 @@
(unspec:X [(match_operand:ANYF 1 "register_operand")
(match_operand:ANYF 2 "register_operand")]
QUIET_COMPARISON))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -2802,19 +2804,19 @@
(define_insn "riscv_frflags"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"frflags\t%0")
(define_insn "riscv_fsflags"
[(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsflags\t%0")
(define_insn "*riscv_fsnvsnan<mode>2"
[(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f")
(match_operand:ANYF 1 "register_operand" "f")]
UNSPECV_FSNVSNAN)]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"feq.<fmt>\tzero,%0,%1"
[(set_attr "type" "fcmp")
(set_attr "mode" "<UNITMODE>")])
--
2.25.1
next prev parent reply other threads:[~2022-10-20 9:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
2022-10-20 9:32 ` [v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension jiawei
2022-10-20 9:32 ` jiawei [this message]
2022-10-20 9:32 ` [v4 PATCH 3/4] RISC-V: Limit regs use for " jiawei
2022-10-27 3:12 ` Kito Cheng
2022-10-20 9:32 ` [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases jiawei
2022-10-30 10:49 ` Andreas Schwab
2022-10-27 3:12 ` [v4 PATCH 0/4] RISC-V: Support z*inx extensions Kito Cheng
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