From: jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@rivosinc.com,
christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn,
Jiawei <jiawei@iscas.ac.cn>
Subject: [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases.
Date: Thu, 20 Oct 2022 17:32:35 +0800 [thread overview]
Message-ID: <20221020093235.5071-5-jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20221020093235.5071-1-jiawei@iscas.ac.cn>
From: Jiawei <jiawei@iscas.ac.cn>
Test zhinx/zhinxmin support, same like with zfh/zfhmin testcases
but use gprs and don't use fmv instruction.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Float16-zhinx-1.c: New test.
* gcc.target/riscv/_Float16-zhinx-2.c: New test.
* gcc.target/riscv/_Float16-zhinx-3.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-1.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-2.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-3.c: New test.
---
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c | 10 ++++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c | 10 ++++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c | 10 ++++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c | 10 ++++++++++
6 files changed, 58 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
new file mode 100644
index 00000000000..90172b57e05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ return b;
+}
+
+/* { dg-final { scan-assembler-not "fmv.h" } } */
+/* { dg-final { scan-assembler-times "mv" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
new file mode 100644
index 00000000000..26f01198c97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fadd.h fa" } } */
+ /* { dg-final { scan-assembler-times "fadd.h a" 1 } } */
+ return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
new file mode 100644
index 00000000000..573913568e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fgt.h fa" } } */
+ /* { dg-final { scan-assembler-times "fgt.h a" 1 } } */
+ return a > b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
new file mode 100644
index 00000000000..0070ebf616c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fmv.h" } } */
+ /* { dg-final { scan-assembler-not "fmv.s" } } */
+ /* { dg-final { scan-assembler-times "mv" 1 } } */
+ return b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
new file mode 100644
index 00000000000..17f45a938d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fadd.h" } } */
+ /* { dg-final { scan-assembler-not "fadd.s fa" } } */
+ /* { dg-final { scan-assembler-times "fadd.s a" 1 } } */
+ return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
new file mode 100644
index 00000000000..7a43641a5a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfhmin -mabi=lp64f -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fgt.h" } } */
+ /* { dg-final { scan-assembler-not "fgt.s fa" } } */
+ /* { dg-final { scan-assembler-times "fgt.s a" 1 } } */
+ return a > b;
+}
--
2.25.1
next prev parent reply other threads:[~2022-10-20 9:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
2022-10-20 9:32 ` [v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension jiawei
2022-10-20 9:32 ` [v4 PATCH 2/4] RISC-V: Target support for " jiawei
2022-10-20 9:32 ` [v4 PATCH 3/4] RISC-V: Limit regs use " jiawei
2022-10-27 3:12 ` Kito Cheng
2022-10-20 9:32 ` jiawei [this message]
2022-10-30 10:49 ` [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases Andreas Schwab
2022-10-27 3:12 ` [v4 PATCH 0/4] RISC-V: Support z*inx extensions Kito Cheng
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