* [PATCH 0/2] Intel Grand Ridge Support @ 2022-11-07 1:41 Haochen Jiang 2022-11-07 1:41 ` [PATCH 1/2] Initial Grand Ridge support Haochen Jiang 2022-11-07 1:41 ` [PATCH 2/2] Add m_CORE_ATOM for atom cores Haochen Jiang 0 siblings, 2 replies; 5+ messages in thread From: Haochen Jiang @ 2022-11-07 1:41 UTC (permalink / raw) To: gcc-patches; +Cc: ubizjak, hongtao.liu Hi all, These patches aimed to add initial Granite Rapids support for GCC. Also we added a new m_CORE_ATOM for future atom core tune. They need to be checked in after RAO-INT patch. The information for Granite Rapids comes following: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] Initial Grand Ridge support 2022-11-07 1:41 [PATCH 0/2] Intel Grand Ridge Support Haochen Jiang @ 2022-11-07 1:41 ` Haochen Jiang 2022-11-07 2:08 ` Hongtao Liu 2022-11-07 1:41 ` [PATCH 2/2] Add m_CORE_ATOM for atom cores Haochen Jiang 1 sibling, 1 reply; 5+ messages in thread From: Haochen Jiang @ 2022-11-07 1:41 UTC (permalink / raw) To: gcc-patches; +Cc: ubizjak, hongtao.liu gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_names): Add grandridge. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h: (enum processor_types): Add INTEL_GRANDRIDGE. * config.gcc: Add -march=grandridge. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle grandridge. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (m_GRANDRIDGE): New define. (processor_cost_table): Add grandridge. * config/i386/i386.h (enum processor_type): Add PROCESSOR_GRANDRIDGE. (PTA_GRANDRIDGE): Ditto. * doc/extend.texi: Add grandridge. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * gcc/testsuite/g++.target/i386/mv16.C: Add grandridge. * gcc.target/i386/funcspec-56.inc: Handle new march. --- gcc/common/config/i386/cpuinfo.h | 6 ++++++ gcc/common/config/i386/i386-common.cc | 3 +++ gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/config.gcc | 2 +- gcc/config/i386/driver-i386.cc | 5 ++++- gcc/config/i386/i386-c.cc | 7 +++++++ gcc/config/i386/i386-options.cc | 2 ++ gcc/config/i386/i386.h | 2 ++ gcc/doc/extend.texi | 3 +++ gcc/doc/invoke.texi | 9 +++++++++ gcc/testsuite/g++.target/i386/mv16.C | 6 ++++++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 + 12 files changed, 45 insertions(+), 2 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index df3500adc83..4d1bcffb978 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -573,6 +573,12 @@ get_intel_cpu (struct __processor_model *cpu_model, cpu_model->__cpu_type = INTEL_COREI7; cpu_model->__cpu_subtype = INTEL_COREI7_GRANITERAPIDS; break; + case 0xb6: + /* Grand Ridge. */ + cpu = "grandridge"; + CHECK___builtin_cpu_is ("grandridge"); + cpu_model->__cpu_type = INTEL_GRANDRIDGE; + break; case 0x17: case 0x1d: /* Penryn. */ diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 60a193a651c..431fd0d3ad1 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -1920,6 +1920,7 @@ const char *const processor_names[] = "goldmont-plus", "tremont", "sierraforest", + "grandridge", "knl", "knm", "skylake", @@ -2071,6 +2072,8 @@ const pta processor_alias_table[] = M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2}, {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST, M_CPU_SUBTYPE (INTEL_SIERRAFOREST), P_PROC_AVX2}, + {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE, + M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2}, {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL, M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F}, {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 345fda648ff..fe2e9e21fd2 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -61,6 +61,7 @@ enum processor_types AMDFAM19H, ZHAOXIN_FAM7H, INTEL_SIERRAFOREST, + INTEL_GRANDRIDGE, CPU_TYPE_MAX, BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX }; diff --git a/gcc/config.gcc b/gcc/config.gcc index 84c040746dc..b5eda046033 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -669,7 +669,7 @@ silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \ skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \ sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \ nano-x2 eden-x4 nano-x4 lujiazui x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \ -sierraforest graniterapids native" +sierraforest graniterapids grandridge native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 3117d83de00..95c16c23c7f 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -591,8 +591,11 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* This is unknown family 0x6 CPU. */ if (has_feature (FEATURE_AVX)) { + /* Assume Grand Ridge. */ + if (has_feature (FEATURE_RAOINT)) + cpu = "grandridge"; /* Assume Granite Rapids. */ - if (has_feature (FEATURE_AMX_FP16)) + else if (has_feature (FEATURE_AMX_FP16)) cpu = "graniterapids"; /* Assume Sierra Forest. */ else if (has_feature (FEATURE_AVXVNNIINT8)) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index a877d24148d..44fab6e80ae 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -206,6 +206,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__sierraforest"); def_or_undef (parse_in, "__sierraforest__"); break; + case PROCESSOR_GRANDRIDGE: + def_or_undef (parse_in, "__grandridge"); + def_or_undef (parse_in, "__grandridge__"); + break; case PROCESSOR_KNL: def_or_undef (parse_in, "__knl"); def_or_undef (parse_in, "__knl__"); @@ -395,6 +399,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_SIERRAFOREST: def_or_undef (parse_in, "__tune_sierraforest__"); break; + case PROCESSOR_GRANDRIDGE: + def_or_undef (parse_in, "__tune_grandridge__"); + break; case PROCESSOR_KNL: def_or_undef (parse_in, "__tune_knl__"); break; diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 3c7570c5edd..23ab1f867d0 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -138,6 +138,7 @@ along with GCC; see the file COPYING3. If not see #define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS) #define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT) #define m_SIERRAFOREST (HOST_WIDE_INT_1U<<PROCESSOR_SIERRAFOREST) +#define m_GRANDRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_GRANDRIDGE) #define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL) #define m_LUJIAZUI (HOST_WIDE_INT_1U<<PROCESSOR_LUJIAZUI) @@ -750,6 +751,7 @@ static const struct processor_costs *processor_cost_table[] = &slm_cost, &tremont_cost, &alderlake_cost, + &alderlake_cost, &slm_cost, &slm_cost, &skylake_cost, diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e3e675d36c5..b32db8da109 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2226,6 +2226,7 @@ enum processor_type PROCESSOR_GOLDMONT_PLUS, PROCESSOR_TREMONT, PROCESSOR_SIERRAFOREST, + PROCESSOR_GRANDRIDGE, PROCESSOR_KNL, PROCESSOR_KNM, PROCESSOR_SKYLAKE, @@ -2351,6 +2352,7 @@ constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD; constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 | PTA_PREFETCHI; +constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT; constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 33a49338bd3..8da0db9770d 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21986,6 +21986,9 @@ Intel Atom Tremont CPU. @item sierraforest Intel Atom Sierra Forest CPU. +@item grandridge +Intel Atom Grand Ridge CPU. + @item knl Intel Knights Landing CPU. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7417f528bb1..f9cd41fac28 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -32080,6 +32080,15 @@ MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support. +@item grandridge +Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, +XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, +MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, +PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD and RAOINT instruction set +support. + @item knl Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C index e0e0f153d1c..772791b96e8 100644 --- a/gcc/testsuite/g++.target/i386/mv16.C +++ b/gcc/testsuite/g++.target/i386/mv16.C @@ -100,6 +100,10 @@ int __attribute__ ((target("arch=graniterapids"))) foo () { return 26; } +int __attribute__ ((target("arch=grandridge"))) foo () { + return 27; +} + int main () { int val = foo (); @@ -142,6 +146,8 @@ int main () assert (val == 25); else if (__builtin_cpu_is ("graniterapids")) assert (val == 26); + else if (__builtin_cpu_is ("grandridge")) + assert (val == 27); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 7eb18c6952d..37802307bcf 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -186,6 +186,7 @@ extern void test_arch_goldmont (void) __attribute__((__target__("arch=goldmont" extern void test_arch_goldmont_plus (void) __attribute__((__target__("arch=goldmont-plus"))); extern void test_arch_tremont (void) __attribute__((__target__("arch=tremont"))); extern void test_arch_sierraforest (void) __attribute__((__target__("arch=sierraforest"))); +extern void test_arch_grandridge (void) __attribute__((__target__("arch=grandridge"))); extern void test_arch_knl (void) __attribute__((__target__("arch=knl"))); extern void test_arch_knm (void) __attribute__((__target__("arch=knm"))); extern void test_arch_skylake (void) __attribute__((__target__("arch=skylake"))); -- 2.18.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] Initial Grand Ridge support 2022-11-07 1:41 ` [PATCH 1/2] Initial Grand Ridge support Haochen Jiang @ 2022-11-07 2:08 ` Hongtao Liu 0 siblings, 0 replies; 5+ messages in thread From: Hongtao Liu @ 2022-11-07 2:08 UTC (permalink / raw) To: Haochen Jiang; +Cc: gcc-patches, ubizjak, hongtao.liu On Mon, Nov 7, 2022 at 9:41 AM Haochen Jiang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > gcc/ChangeLog: > > * common/config/i386/i386-common.cc > (processor_names): Add grandridge. > (processor_alias_table): Ditto. > * common/config/i386/i386-cpuinfo.h: > (enum processor_types): Add INTEL_GRANDRIDGE. > * config.gcc: Add -march=grandridge. > * config/i386/driver-i386.cc (host_detect_local_cpu): > Handle grandridge. > * config/i386/i386-c.cc (ix86_target_macros_internal): > Ditto. > * config/i386/i386-options.cc (m_GRANDRIDGE): New define. > (processor_cost_table): Add grandridge. > * config/i386/i386.h (enum processor_type): > Add PROCESSOR_GRANDRIDGE. > (PTA_GRANDRIDGE): Ditto. > * doc/extend.texi: Add grandridge. > * doc/invoke.texi: Ditto. > > gcc/testsuite/ChangeLog: > > * gcc/testsuite/g++.target/i386/mv16.C: Add grandridge. > * gcc.target/i386/funcspec-56.inc: Handle new march. > --- LGTM. > gcc/common/config/i386/cpuinfo.h | 6 ++++++ > gcc/common/config/i386/i386-common.cc | 3 +++ > gcc/common/config/i386/i386-cpuinfo.h | 1 + > gcc/config.gcc | 2 +- > gcc/config/i386/driver-i386.cc | 5 ++++- > gcc/config/i386/i386-c.cc | 7 +++++++ > gcc/config/i386/i386-options.cc | 2 ++ > gcc/config/i386/i386.h | 2 ++ > gcc/doc/extend.texi | 3 +++ > gcc/doc/invoke.texi | 9 +++++++++ > gcc/testsuite/g++.target/i386/mv16.C | 6 ++++++ > gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 + > 12 files changed, 45 insertions(+), 2 deletions(-) > > diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h > index df3500adc83..4d1bcffb978 100644 > --- a/gcc/common/config/i386/cpuinfo.h > +++ b/gcc/common/config/i386/cpuinfo.h > @@ -573,6 +573,12 @@ get_intel_cpu (struct __processor_model *cpu_model, > cpu_model->__cpu_type = INTEL_COREI7; > cpu_model->__cpu_subtype = INTEL_COREI7_GRANITERAPIDS; > break; > + case 0xb6: > + /* Grand Ridge. */ > + cpu = "grandridge"; > + CHECK___builtin_cpu_is ("grandridge"); > + cpu_model->__cpu_type = INTEL_GRANDRIDGE; > + break; > case 0x17: > case 0x1d: > /* Penryn. */ > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > index 60a193a651c..431fd0d3ad1 100644 > --- a/gcc/common/config/i386/i386-common.cc > +++ b/gcc/common/config/i386/i386-common.cc > @@ -1920,6 +1920,7 @@ const char *const processor_names[] = > "goldmont-plus", > "tremont", > "sierraforest", > + "grandridge", > "knl", > "knm", > "skylake", > @@ -2071,6 +2072,8 @@ const pta processor_alias_table[] = > M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2}, > {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST, > M_CPU_SUBTYPE (INTEL_SIERRAFOREST), P_PROC_AVX2}, > + {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE, > + M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2}, > {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL, > M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F}, > {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM, > diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h > index 345fda648ff..fe2e9e21fd2 100644 > --- a/gcc/common/config/i386/i386-cpuinfo.h > +++ b/gcc/common/config/i386/i386-cpuinfo.h > @@ -61,6 +61,7 @@ enum processor_types > AMDFAM19H, > ZHAOXIN_FAM7H, > INTEL_SIERRAFOREST, > + INTEL_GRANDRIDGE, > CPU_TYPE_MAX, > BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX > }; > diff --git a/gcc/config.gcc b/gcc/config.gcc > index 84c040746dc..b5eda046033 100644 > --- a/gcc/config.gcc > +++ b/gcc/config.gcc > @@ -669,7 +669,7 @@ silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \ > skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \ > sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \ > nano-x2 eden-x4 nano-x4 lujiazui x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \ > -sierraforest graniterapids native" > +sierraforest graniterapids grandridge native" > > # Additional x86 processors supported by --with-cpu=. Each processor > # MUST be separated by exactly one space. > diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc > index 3117d83de00..95c16c23c7f 100644 > --- a/gcc/config/i386/driver-i386.cc > +++ b/gcc/config/i386/driver-i386.cc > @@ -591,8 +591,11 @@ const char *host_detect_local_cpu (int argc, const char **argv) > /* This is unknown family 0x6 CPU. */ > if (has_feature (FEATURE_AVX)) > { > + /* Assume Grand Ridge. */ > + if (has_feature (FEATURE_RAOINT)) > + cpu = "grandridge"; > /* Assume Granite Rapids. */ > - if (has_feature (FEATURE_AMX_FP16)) > + else if (has_feature (FEATURE_AMX_FP16)) > cpu = "graniterapids"; > /* Assume Sierra Forest. */ > else if (has_feature (FEATURE_AVXVNNIINT8)) > diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc > index a877d24148d..44fab6e80ae 100644 > --- a/gcc/config/i386/i386-c.cc > +++ b/gcc/config/i386/i386-c.cc > @@ -206,6 +206,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, > def_or_undef (parse_in, "__sierraforest"); > def_or_undef (parse_in, "__sierraforest__"); > break; > + case PROCESSOR_GRANDRIDGE: > + def_or_undef (parse_in, "__grandridge"); > + def_or_undef (parse_in, "__grandridge__"); > + break; > case PROCESSOR_KNL: > def_or_undef (parse_in, "__knl"); > def_or_undef (parse_in, "__knl__"); > @@ -395,6 +399,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, > case PROCESSOR_SIERRAFOREST: > def_or_undef (parse_in, "__tune_sierraforest__"); > break; > + case PROCESSOR_GRANDRIDGE: > + def_or_undef (parse_in, "__tune_grandridge__"); > + break; > case PROCESSOR_KNL: > def_or_undef (parse_in, "__tune_knl__"); > break; > diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc > index 3c7570c5edd..23ab1f867d0 100644 > --- a/gcc/config/i386/i386-options.cc > +++ b/gcc/config/i386/i386-options.cc > @@ -138,6 +138,7 @@ along with GCC; see the file COPYING3. If not see > #define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS) > #define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT) > #define m_SIERRAFOREST (HOST_WIDE_INT_1U<<PROCESSOR_SIERRAFOREST) > +#define m_GRANDRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_GRANDRIDGE) > #define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL) > > #define m_LUJIAZUI (HOST_WIDE_INT_1U<<PROCESSOR_LUJIAZUI) > @@ -750,6 +751,7 @@ static const struct processor_costs *processor_cost_table[] = > &slm_cost, > &tremont_cost, > &alderlake_cost, > + &alderlake_cost, > &slm_cost, > &slm_cost, > &skylake_cost, > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > index e3e675d36c5..b32db8da109 100644 > --- a/gcc/config/i386/i386.h > +++ b/gcc/config/i386/i386.h > @@ -2226,6 +2226,7 @@ enum processor_type > PROCESSOR_GOLDMONT_PLUS, > PROCESSOR_TREMONT, > PROCESSOR_SIERRAFOREST, > + PROCESSOR_GRANDRIDGE, > PROCESSOR_KNL, > PROCESSOR_KNM, > PROCESSOR_SKYLAKE, > @@ -2351,6 +2352,7 @@ constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA > | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD; > constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 > | PTA_PREFETCHI; > +constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT; > constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW > | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; > constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 33a49338bd3..8da0db9770d 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -21986,6 +21986,9 @@ Intel Atom Tremont CPU. > @item sierraforest > Intel Atom Sierra Forest CPU. > > +@item grandridge > +Intel Atom Grand Ridge CPU. > + > @item knl > Intel Knights Landing CPU. > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 7417f528bb1..f9cd41fac28 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -32080,6 +32080,15 @@ MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, > PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, > AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support. > > +@item grandridge > +Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, > +SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, > +XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, > +MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, > +PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, > +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD and RAOINT instruction set > +support. > + > @item knl > Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, > SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, > diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C > index e0e0f153d1c..772791b96e8 100644 > --- a/gcc/testsuite/g++.target/i386/mv16.C > +++ b/gcc/testsuite/g++.target/i386/mv16.C > @@ -100,6 +100,10 @@ int __attribute__ ((target("arch=graniterapids"))) foo () { > return 26; > } > > +int __attribute__ ((target("arch=grandridge"))) foo () { > + return 27; > +} > + > int main () > { > int val = foo (); > @@ -142,6 +146,8 @@ int main () > assert (val == 25); > else if (__builtin_cpu_is ("graniterapids")) > assert (val == 26); > + else if (__builtin_cpu_is ("grandridge")) > + assert (val == 27); > else > assert (val == 0); > > diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc > index 7eb18c6952d..37802307bcf 100644 > --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc > +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc > @@ -186,6 +186,7 @@ extern void test_arch_goldmont (void) __attribute__((__target__("arch=goldmont" > extern void test_arch_goldmont_plus (void) __attribute__((__target__("arch=goldmont-plus"))); > extern void test_arch_tremont (void) __attribute__((__target__("arch=tremont"))); > extern void test_arch_sierraforest (void) __attribute__((__target__("arch=sierraforest"))); > +extern void test_arch_grandridge (void) __attribute__((__target__("arch=grandridge"))); > extern void test_arch_knl (void) __attribute__((__target__("arch=knl"))); > extern void test_arch_knm (void) __attribute__((__target__("arch=knm"))); > extern void test_arch_skylake (void) __attribute__((__target__("arch=skylake"))); > -- > 2.18.1 > -- BR, Hongtao ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] Add m_CORE_ATOM for atom cores 2022-11-07 1:41 [PATCH 0/2] Intel Grand Ridge Support Haochen Jiang 2022-11-07 1:41 ` [PATCH 1/2] Initial Grand Ridge support Haochen Jiang @ 2022-11-07 1:41 ` Haochen Jiang 2022-11-07 9:13 ` Uros Bizjak 1 sibling, 1 reply; 5+ messages in thread From: Haochen Jiang @ 2022-11-07 1:41 UTC (permalink / raw) To: gcc-patches; +Cc: ubizjak, hongtao.liu gcc/ChangeLog: * config/i386/i386-options.cc (m_CORE_ATOM): New. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Initial tune for CORE_ATOM. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_DEST_FALSE_DEP_FOR_GLC): Ditto. (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. (X86_TUNE_USE_LEAVE): Ditto. (X86_TUNE_PUSH_MEMORY): Ditto. (X86_TUNE_USE_INCDEC): Ditto. (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. (X86_TUNE_USE_SAHF): Ditto. (X86_TUNE_USE_BT): Ditto. (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. (X86_TUNE_ONE_IF_CONV_INSN): Ditto. (X86_TUNE_AVOID_MFENCE): Ditto. (X86_TUNE_USE_SIMODE_FIOP): Ditto. (X86_TUNE_EXT_80387_CONSTANTS): Ditto. (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. (X86_TUNE_SSE_TYPELESS_STORES): Ditto. (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. (X86_TUNE_AVOID_4BYTE_PREFIXES): Ditto. (X86_TUNE_USE_GATHER_2PARTS): Ditto. (X86_TUNE_USE_GATHER_4PARTS): Ditto. (X86_TUNE_USE_GATHER): Ditto. --- gcc/config/i386/i386-options.cc | 1 + gcc/config/i386/x86-tune.def | 71 +++++++++++++++++++-------------- 2 files changed, 41 insertions(+), 31 deletions(-) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 23ab1f867d0..e5c77f3a84d 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -139,6 +139,7 @@ along with GCC; see the file COPYING3. If not see #define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT) #define m_SIERRAFOREST (HOST_WIDE_INT_1U<<PROCESSOR_SIERRAFOREST) #define m_GRANDRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_GRANDRIDGE) +#define m_CORE_ATOM (m_SIERRAFOREST | m_GRANDRIDGE) #define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL) #define m_LUJIAZUI (HOST_WIDE_INT_1U<<PROCESSOR_LUJIAZUI) diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 540e45d02f9..58e29e7806a 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -42,7 +42,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see DEF_TUNE (X86_TUNE_SCHEDULE, "schedule", m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM + | m_GENERIC) /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming on modern chips. Prefer stores affecting whole integer register @@ -52,7 +53,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency", m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL | m_KNL | m_KNM | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT - | m_ALDERLAKE | m_GENERIC) + | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store destinations to be 128bit to allow register renaming on 128bit SSE units, @@ -63,7 +64,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency", DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10 | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE - | m_GENERIC) + | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids partial write to the destination in scalar SSE conversion from FP @@ -71,20 +72,23 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency", DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY, "sse_partial_reg_fp_converts_dependency", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10 - | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_GENERIC) + | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_CORE_ATOM + | m_GENERIC) /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial write to the destination in scalar SSE conversion from integer to FP. */ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY, "sse_partial_reg_converts_dependency", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10 - | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_GENERIC) + | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_CORE_ATOM + | m_GENERIC) /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before several insns to break false dependency on the dest register for GLC micro-architecture. */ DEF_TUNE (X86_TUNE_DEST_FALSE_DEP_FOR_GLC, - "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE) + "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE + | m_CORE_ATOM) /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies are resolved on SSE register parts instead of whole registers, so we may @@ -110,14 +114,14 @@ DEF_TUNE (X86_TUNE_MOVX, "movx", m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI - | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by full sized loads. */ DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall", m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent conditional jump instruction for 32 bit TARGET. */ @@ -173,14 +177,14 @@ DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move", /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */ DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave", m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI - | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions. Some chips, like 486 and Pentium works faster with separate load and push instructions. */ DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory", m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred over esp subtraction. */ @@ -250,15 +254,16 @@ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO)) DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec", ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT - | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI - | m_GENERIC)) + | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM + | m_LUJIAZUI | m_GENERIC)) /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred for DFmode copies */ DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves", ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)) + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE + | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag will impact LEA instruction selection. */ @@ -296,7 +301,8 @@ DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA) move/set sequences of bytes with known size. */ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB, "prefer_known_rep_movsb_stosb", - m_SKYLAKE | m_ALDERLAKE | m_TREMONT | m_CORE_AVX512 | m_LUJIAZUI) + m_SKYLAKE | m_ALDERLAKE | m_CORE_ATOM | m_TREMONT | m_CORE_AVX512 + | m_LUJIAZUI) /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of compact prologues and epilogues by issuing a misaligned moves. This @@ -306,14 +312,14 @@ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB, DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES, "misaligned_move_string_pro_epilogues", m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT - | m_ALDERLAKE | m_GENERIC) + | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_USE_SAHF: Controls use of SAHF. */ DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS - | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */ DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", @@ -324,13 +330,13 @@ DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", DEF_TUNE (X86_TUNE_USE_BT, "use_bt", m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_LAKEMONT | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT - | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency for bit-manipulation instructions. */ DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi", - m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI - | m_GENERIC) + m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM + | m_LUJIAZUI | m_GENERIC) /* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based on hardware capabilities. Bdver3 hardware has a loop buffer which makes @@ -342,12 +348,13 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4) if-converted sequence to one. */ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn", m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT - | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI | m_GENERIC) + | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_LUJIAZUI + | m_GENERIC) /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */ DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence", m_CORE_ALL | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE - | m_GENERIC) + | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) - @@ -372,7 +379,7 @@ DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop", ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT - | m_ALDERLAKE | m_GENERIC)) + | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) @@ -381,7 +388,8 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_LUJIAZUI - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM + | m_GENERIC) /*****************************************************************************/ /* SSE instruction selection tuning */ @@ -397,14 +405,15 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) + | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI + | m_GENERIC) /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) + | m_CORE_ATOM | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single precision 128bit instructions instead of double where possible. */ @@ -414,13 +423,13 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */ DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores", m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_ALDERLAKE - | m_GENERIC) + | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to xorps/xorpd and other variants. */ DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer to SSE registers. If disabled, the moves will be done by storing @@ -467,22 +476,22 @@ DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb", /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */ DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes", m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_INTEL) + | m_CORE_ATOM | m_INTEL) /* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2 elements. */ DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts", - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_GENERIC)) + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4 elements. */ DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts", - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_GENERIC)) + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more elements. */ DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather", - ~(m_ZNVER1 | m_ZNVER2 | m_ALDERLAKE | m_GENERIC)) + ~(m_ZNVER1 | m_ZNVER2 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or smaller FMA chain. */ -- 2.18.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] Add m_CORE_ATOM for atom cores 2022-11-07 1:41 ` [PATCH 2/2] Add m_CORE_ATOM for atom cores Haochen Jiang @ 2022-11-07 9:13 ` Uros Bizjak 0 siblings, 0 replies; 5+ messages in thread From: Uros Bizjak @ 2022-11-07 9:13 UTC (permalink / raw) To: Haochen Jiang; +Cc: gcc-patches, hongtao.liu On Mon, Nov 7, 2022 at 2:41 AM Haochen Jiang <haochen.jiang@intel.com> wrote: > > gcc/ChangeLog: > > * config/i386/i386-options.cc (m_CORE_ATOM): New. > * config/i386/x86-tune.def > (X86_TUNE_SCHEDULE): Initial tune for CORE_ATOM. > (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. > (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. > (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. > (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. > (X86_TUNE_DEST_FALSE_DEP_FOR_GLC): Ditto. > (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. > (X86_TUNE_USE_LEAVE): Ditto. > (X86_TUNE_PUSH_MEMORY): Ditto. > (X86_TUNE_USE_INCDEC): Ditto. > (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. > (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. > (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. > (X86_TUNE_USE_SAHF): Ditto. > (X86_TUNE_USE_BT): Ditto. > (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. > (X86_TUNE_ONE_IF_CONV_INSN): Ditto. > (X86_TUNE_AVOID_MFENCE): Ditto. > (X86_TUNE_USE_SIMODE_FIOP): Ditto. > (X86_TUNE_EXT_80387_CONSTANTS): Ditto. > (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. > (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. > (X86_TUNE_SSE_TYPELESS_STORES): Ditto. > (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. > (X86_TUNE_AVOID_4BYTE_PREFIXES): Ditto. > (X86_TUNE_USE_GATHER_2PARTS): Ditto. > (X86_TUNE_USE_GATHER_4PARTS): Ditto. > (X86_TUNE_USE_GATHER): Ditto. OK. Thanks, Uros. > --- > gcc/config/i386/i386-options.cc | 1 + > gcc/config/i386/x86-tune.def | 71 +++++++++++++++++++-------------- > 2 files changed, 41 insertions(+), 31 deletions(-) > > diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc > index 23ab1f867d0..e5c77f3a84d 100644 > --- a/gcc/config/i386/i386-options.cc > +++ b/gcc/config/i386/i386-options.cc > @@ -139,6 +139,7 @@ along with GCC; see the file COPYING3. If not see > #define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT) > #define m_SIERRAFOREST (HOST_WIDE_INT_1U<<PROCESSOR_SIERRAFOREST) > #define m_GRANDRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_GRANDRIDGE) > +#define m_CORE_ATOM (m_SIERRAFOREST | m_GRANDRIDGE) > #define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL) > > #define m_LUJIAZUI (HOST_WIDE_INT_1U<<PROCESSOR_LUJIAZUI) > diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def > index 540e45d02f9..58e29e7806a 100644 > --- a/gcc/config/i386/x86-tune.def > +++ b/gcc/config/i386/x86-tune.def > @@ -42,7 +42,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > DEF_TUNE (X86_TUNE_SCHEDULE, "schedule", > m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT > | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI > - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM > + | m_GENERIC) > > /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming > on modern chips. Prefer stores affecting whole integer register > @@ -52,7 +53,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency", > m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 > | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL > | m_KNL | m_KNM | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT > - | m_ALDERLAKE | m_GENERIC) > + | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store > destinations to be 128bit to allow register renaming on 128bit SSE units, > @@ -63,7 +64,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency", > DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency", > m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10 > | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE > - | m_GENERIC) > + | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids > partial write to the destination in scalar SSE conversion from FP > @@ -71,20 +72,23 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency", > DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY, > "sse_partial_reg_fp_converts_dependency", > m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10 > - | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_GENERIC) > + | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_CORE_ATOM > + | m_GENERIC) > > /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial > write to the destination in scalar SSE conversion from integer to FP. */ > DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY, > "sse_partial_reg_converts_dependency", > m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10 > - | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_GENERIC) > + | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_CORE_ATOM > + | m_GENERIC) > > /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before > several insns to break false dependency on the dest register for GLC > micro-architecture. */ > DEF_TUNE (X86_TUNE_DEST_FALSE_DEP_FOR_GLC, > - "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE) > + "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE > + | m_CORE_ATOM) > > /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies > are resolved on SSE register parts instead of whole registers, so we may > @@ -110,14 +114,14 @@ DEF_TUNE (X86_TUNE_MOVX, "movx", > m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE > | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL > | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI > - | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by > full sized loads. */ > DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall", > m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL > | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE > - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent > conditional jump instruction for 32 bit TARGET. */ > @@ -173,14 +177,14 @@ DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move", > /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */ > DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave", > m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI > - | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions. > Some chips, like 486 and Pentium works faster with separate load > and push instructions. */ > DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory", > m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE > - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred > over esp subtraction. */ > @@ -250,15 +254,16 @@ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO)) > DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec", > ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE > | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT > - | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI > - | m_GENERIC)) > + | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM > + | m_LUJIAZUI | m_GENERIC)) > > /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred > for DFmode copies */ > DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves", > ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT > | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI > - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)) > + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE > + | m_CORE_ATOM | m_GENERIC)) > > /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag > will impact LEA instruction selection. */ > @@ -296,7 +301,8 @@ DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA) > move/set sequences of bytes with known size. */ > DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB, > "prefer_known_rep_movsb_stosb", > - m_SKYLAKE | m_ALDERLAKE | m_TREMONT | m_CORE_AVX512 | m_LUJIAZUI) > + m_SKYLAKE | m_ALDERLAKE | m_CORE_ATOM | m_TREMONT | m_CORE_AVX512 > + | m_LUJIAZUI) > > /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of > compact prologues and epilogues by issuing a misaligned moves. This > @@ -306,14 +312,14 @@ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB, > DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES, > "misaligned_move_string_pro_epilogues", > m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT > - | m_ALDERLAKE | m_GENERIC) > + | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_USE_SAHF: Controls use of SAHF. */ > DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf", > m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT > | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER > | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS > - | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */ > DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", > @@ -324,13 +330,13 @@ DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", > DEF_TUNE (X86_TUNE_USE_BT, "use_bt", > m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL > | m_LAKEMONT | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT > - | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency > for bit-manipulation instructions. */ > DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi", > - m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI > - | m_GENERIC) > + m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM > + | m_LUJIAZUI | m_GENERIC) > > /* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based > on hardware capabilities. Bdver3 hardware has a loop buffer which makes > @@ -342,12 +348,13 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4) > if-converted sequence to one. */ > DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn", > m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT > - | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI | m_GENERIC) > + | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_LUJIAZUI > + | m_GENERIC) > > /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */ > DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence", > m_CORE_ALL | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE > - | m_GENERIC) > + | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by > generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) - > @@ -372,7 +379,7 @@ DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop", > ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL > | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE > | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT > - | m_ALDERLAKE | m_GENERIC)) > + | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) > > /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */ > DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) > @@ -381,7 +388,8 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) > DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants", > m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT > | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_LUJIAZUI > - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM > + | m_GENERIC) > > /*****************************************************************************/ > /* SSE instruction selection tuning */ > @@ -397,14 +405,15 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", > DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", > m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM > | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE > - | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) > + | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI > + | m_GENERIC) > > /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores > instead of a sequence loading registers by parts. */ > DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", > m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM > | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE > - | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) > + | m_CORE_ATOM | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) > > /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single > precision 128bit instructions instead of double where possible. */ > @@ -414,13 +423,13 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim > /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */ > DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores", > m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_ALDERLAKE > - | m_GENERIC) > + | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to > xorps/xorpd and other variants. */ > DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor", > m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER > - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC) > + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) > > /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer > to SSE registers. If disabled, the moves will be done by storing > @@ -467,22 +476,22 @@ DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb", > /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */ > DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes", > m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE > - | m_INTEL) > + | m_CORE_ATOM | m_INTEL) > > /* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2 > elements. */ > DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts", > - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_GENERIC)) > + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) > > /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4 > elements. */ > DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts", > - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_GENERIC)) > + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) > > /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more > elements. */ > DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather", > - ~(m_ZNVER1 | m_ZNVER2 | m_ALDERLAKE | m_GENERIC)) > + ~(m_ZNVER1 | m_ZNVER2 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) > > /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or > smaller FMA chain. */ > -- > 2.18.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-11-07 9:13 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-07 1:41 [PATCH 0/2] Intel Grand Ridge Support Haochen Jiang 2022-11-07 1:41 ` [PATCH 1/2] Initial Grand Ridge support Haochen Jiang 2022-11-07 2:08 ` Hongtao Liu 2022-11-07 1:41 ` [PATCH 2/2] Add m_CORE_ATOM for atom cores Haochen Jiang 2022-11-07 9:13 ` Uros Bizjak
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