From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Vineet Gupta <vineetg@rivosinc.com>,
Jeff Law <jlaw@ventanamicro.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH] RISC-V: costs: handle BSWAP
Date: Tue, 8 Nov 2022 20:54:15 +0100 [thread overview]
Message-ID: <20221108195415.2701208-1-philipp.tomsich@vrull.eu> (raw)
The BSWAP operation is not handled in rtx_costs. Add it.
With Zbb, BSWAP for XLEN is a single instruction; for smaller modes,
it will expand into two.
gcc/ChangeLog:
* config/riscv/riscv.c (rtx_costs): Add BSWAP.
---
gcc/config/riscv/riscv.cc | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32f9ef9ade9..ab6c745c722 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2562,6 +2562,16 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
return false;
+ case BSWAP:
+ if (TARGET_ZBB)
+ {
+ /* RISC-V only defines rev8 for XLEN, so we will need an extra
+ shift-right instruction for smaller modes. */
+ *total = COSTS_N_INSNS (mode == word_mode ? 1 : 2);
+ return true;
+ }
+ return false;
+
case FLOAT:
case UNSIGNED_FLOAT:
case FIX:
--
2.34.1
next reply other threads:[~2022-11-08 19:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 19:54 Philipp Tomsich [this message]
2022-11-09 2:57 ` Jeff Law
2022-11-09 3:15 ` Palmer Dabbelt
2022-11-09 4:43 ` Andrew Pinski
2022-11-09 4:53 ` Palmer Dabbelt
2022-11-09 9:27 ` Philipp Tomsich
2022-11-09 9:33 ` Philipp Tomsich
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