From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Kito Cheng <kito.cheng@gmail.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Jeff Law <jlaw@ventanamicro.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH] RISC-V: Fix selection of pipeline model for sifive-7-series
Date: Thu, 10 Nov 2022 00:49:48 +0100 [thread overview]
Message-ID: <20221109234948.3279391-1-philipp.tomsich@vrull.eu> (raw)
A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
while now, due to the pipeline model for sifive-7-series not being
selected despite -mtune=sifive-7-series. The root cause is that the
respective RISCV_TUNE entry points to generic instead. Fix this.
Fixes 97d1ed67fc6 ("RISC-V: Support --target-help for -mcpu/-mtune")
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Update
sifive-7-series to point to the sifive_7 pipeline
description.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
gcc/config/riscv/riscv-cores.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index b84ad999ac1..31ad34682c5 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -36,7 +36,7 @@
RISCV_TUNE("rocket", generic, rocket_tune_info)
RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
-RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info)
+RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)
--
2.34.1
next reply other threads:[~2022-11-09 23:49 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 23:49 Philipp Tomsich [this message]
2022-11-10 1:03 ` Kito Cheng
2022-11-10 13:58 ` Philipp Tomsich
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